Heterogate junctionless tunnel field-effect transistor: future of low-power devices

Rahi, Shiromani Balmukund; Asthana, Pranav Kumar; Gupta, Shoubhik

doi:10.1007/s10825-016-0936-9

Cited by 49 publications

(23 citation statements)

References 32 publications

(51 reference statements)

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“…Another possibility of temperature-dependent threshold voltage shift is work function change of back and top gate with temperature. According to simulation studies [23][24][25] , work function change of gate in our devices can induce threshold voltage shift with constant SS and I off. To determine the accurate mechanism of temperature-dependent threshold voltage shift in our BP NHJ-TFETs requires further systematic studies in the future.…”

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confidence: 91%

Thickness-controlled black phosphorus tunnel field-effect transistor for low-power switches

et al. 2020

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The continuous transistor down-scaling has been the key to the successful development of the current information technology. However, with Moore's law reaching its limits the development of alternative transistor architectures is urgently needed 1 . Transistors require at least 60 mV switching voltage for each 10-fold current increase, i.e. subthreshold swing (SS) 60 mV/dec. Alternative tunnel field-effect transistors (TFETs) are widely studied to achieve a sub-thermionic SS and high I 60 (current where SS becomes 60 mV/dec) 2 . Heterojunction (HJ) TFETs bear promise to deliver high I 60 , but experimental results do not meet theoretical expectations due to interface problems in the HJs constructed from different materials. Here, we report a natural HJ-TFET with spatially varying layer thickness in black phosphorus (BP) without interface problems. We achieved record-low average SS over 4-5 decades of current, SS ave_4dec ≈ 22.9 mV/dec and SS ave_5dec ≈ 26.0 mV/dec with record-high I 60 (= 0.65-1 μA/μm), paving the way for the application in low power switches.

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confidence: 91%

Thickness-controlled black phosphorus tunnel field-effect transistor for low-power switches

et al. 2020

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“…For minimalism, quantum effects are not obviously constituted in the work except otherwise highlighted. The simulation setup of device parameters and values are presented in Table 1 [8], [14]. These devices get the same surface area, but in contrast with the TFET, the HTFET has a greater cross-sectional tunnel area.…”

Section: (B)double Gate Htfetmentioning

confidence: 99%

Performance Analysis of Double Gate Hetero Junction Tunnel Fet

2019

IJITEE

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In this paper, a novel heterojunction tunnel field-effect transistor (HTFET) using Sentaurus technology computer-aided design (TCAD) simulations has been presented. The InAs/GaSb compound materials are used in both single gate heterojunction TFET (SG-HTFET) and Double gate heterojunction TFET (DG-HTFET) with SiO2 gate oxide layer to increase performance of the device.The implemented SG-HTFET and DG-HTFET device are increase the TFET's cross-sectional tunnel area. This result develops the subthreshold swing (SS) by 2.45 times, drive current (ION) is close to 10-6 A/µm, leakage current (IOFF) is close to 10-17 A/µm and also diminish the ambipolarity of the device compared to the TFET.

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“…The doping profile of N + -I-N + -P + TFET is formed by electrical doped concept rather than physical doping. High-k dielectric was also used to improve the subthreshold swing and on-state current [15]. The rest of the device design parameters used in the simulations are listed in Table 1.…”

Section: Device Structure and Simulationmentioning

confidence: 99%

“…Hence, it can be solved using low bandgap semiconductors [13]. Lately, different methods of improving the performance of TFETs have been presented such as gate engineering [14], using heterostructures and high-k dielectric [15]. TFETs also suffer from ambipolar behavior [16,17], which is concluded from the presence of symmetric areas of P + and N + in the source and the drain, the overlapping between the valence band of the channel, and the conduction band of the drain under negative gate bias.…”

Section: Introductionmentioning

confidence: 99%

Representation of heterostructure electrically doped nanoscale tunnel FET with Gaussian-doping profile for high-performance low-power applications

2018

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In this paper, a gallium antimonide junctionless tunnel field-effect transistor based on electrically doped concept (GaSb-EDTFET) is studied and simulated. The performance of the device is analyzed based on the energy band diagram and electric field profile. The on-current, transconductance, and cutoff frequency are enhanced in case of GaSb-EDTFET compared with Si-EDTFET due to the combination of the high tunneling efficiency of the narrow bandgap and the high-electron mobility of GaSb. On the other hand, the Gaussian-doping profile decreases the ambipolar and off current by increasing the tunneling barrier length at the drain/channel interface. Hence, applying Gaussian-doping profile on GaSb-EDTFET makes it a suitable candidate for analog and digital applications. Next, heterostructure channel/source interface EDTFET is studied which uses GaSb for the source and AlGaSb for the drain and channel regions. Then, it has been optimized by numerical simulation in terms of aluminum (Al) composition. The optimal Al composition was founded to be around 10% (x = 0.1). It is shown that the blend of Gaussian-doping profile and the heterostructure channel/source interface with optimal Al composition remarkably reduces ambipolar current amount to a value of 1.3 × 10 −23 A/μm. The improvements in terms of I off , I on , I on /I off rate, subthreshold swing, transconductance, cutoff frequency, and also suppressed ambipolar behavior are illustrated by numerical simulations.

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Heterogate junctionless tunnel field-effect transistor: future of low-power devices

Cited by 49 publications

References 32 publications

Thickness-controlled black phosphorus tunnel field-effect transistor for low-power switches

Thickness-controlled black phosphorus tunnel field-effect transistor for low-power switches

Performance Analysis of Double Gate Hetero Junction Tunnel Fet

Representation of heterostructure electrically doped nanoscale tunnel FET with Gaussian-doping profile for high-performance low-power applications

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