The continuous transistor down-scaling has been the key to the successful development of the current information technology. However, with Moore's law reaching its limits the development of alternative transistor architectures is urgently needed 1 . Transistors require at least 60 mV switching voltage for each 10-fold current increase, i.e. subthreshold swing (SS) 60 mV/dec. Alternative tunnel field-effect transistors (TFETs) are widely studied to achieve a sub-thermionic SS and high I 60 (current where SS becomes 60 mV/dec) 2 . Heterojunction (HJ) TFETs bear promise to deliver high I 60 , but experimental results do not meet theoretical expectations due to interface problems in the HJs constructed from different materials. Here, we report a natural HJ-TFET with spatially varying layer thickness in black phosphorus (BP) without interface problems. We achieved record-low average SS over 4-5 decades of current, SS ave_4dec ≈ 22.9 mV/dec and SS ave_5dec ≈ 26.0 mV/dec with record-high I 60 (= 0.65-1 μA/μm), paving the way for the application in low power switches.

We report the observation of current-induced spin polarization, the Rashba-Edelstein effect (REE), and its Onsager reciprocal phenomenon, the spin galvanic effect (SGE), in a few-layer graphene/2H-TaS2 heterostructure at room temperature. Spin-sensitive electrical measurements unveil full spin-polarization reversal by an applied gate voltage. The observed gate-tunable chargeto-spin conversion is explained by the ideal work function mismatch between 2H-TaS2 and graphene, which allows strong interface-induced Bychkov-Rashba interaction with a spin-gap reaching 70 meV, while keeping the Dirac nature of the spectrum intact across electron and hole sectors. The reversible electrical generation and control of the nonequilibrium spin polarization vector, not previously observed in a nonmagnetic material, are elegant manifestations of emergent 2D Dirac fermions with robust spin-helical structure. Our experimental findings, supported by first-principles relativistic electronic structure and transport calculations, demonstrate a route to design low-power spin-logic circuits from layered materials.

Transistor downscaling by Moore’s law has facilitated drastic improvements in information technology, but this trend cannot continue because power consumption issues have pushed Moore’s law to its limit. Tunnel field-effect transistors (TFETs) have been suggested to address these issues; however, so far they have not achieved the essential criteria for fast, low-power switches, i.e., an average subthreshold swing over four decades of current (SSave_4dec) below 60 mV/dec and a current of 1–10 μA/μm where the SS is 60 mV/dec (I 60). Here, we report a black phosphorus (BP) heterojunction (HJ) TFET that exhibits a record high I 60 of 19.5 μA/μm and subthermionic SSave_4dec of 37.6 mV/dec at 300 K, using a key material factor, monolayer hexagonal boron nitride tunnel barrier for the drain contact. This work, demonstrating the influence of the tunnel barrier contact on device performance, paves the way for the development of ultrafast low-power logic circuits beyond CMOS capabilities.

An increase in power consumption necessitates a low-power circuit technology to extend Moore’s law. Low-power transistors, such as tunnel field-effect transistors (TFETs), negative-capacitance field-effect transistors (NC-FETs), and Dirac-source field-effect transistors (DS-FETs), have been realised to break the thermionic limit of the subthreshold swing (SS). However, a low-power rectifier, able to overcome the thermionic limit of an ideality factor (η) of 1 at room temperature, has not been proposed yet. In this study, we have realised a DS diode based on graphene/MoS2/graphite van der Waals heterostructures, which exhibits a steep-slope characteristic curve, by exploiting the linear density of states (DOSs) of graphene. For the developed DS diode, we obtained η < 1 for more than four decades of drain current (ηave_4dec < 1) with a minimum value of 0.8, and a rectifying ratio exceeding 108. The realisation of a DS diode represents an additional step towards the development of low-power electronic circuits.

Reductions in transistor size have improved functionality of transistors and lowered costs of electronic processors. However, as transistors decrease in size, quantum tunneling causes increased leakage currents and power consumption. To resolve power consumption issues, tunnel field-effect transistors (TFETs) utilizing band-to-band tunneling (BTBT) have been suggested. Such devices can overcome the 60 mV/dec subthreshold swing (SS) limit that is a disadvantage of conventional metal-oxide-semiconductor field-effect transistors (MOS-FETs), but only a limited number of TFETs have achieved this at 300 K. Here, we report complementary trilayer−bulk black phosphorus (BP) heterojunction TFETs with an SS min of 17.7 mV/dec (21.3 mV/dec) for p-type (n-type) operation. In the same devices, SS ≫ 60 mV/dec is exhibited when BTBT occurs within the trilayer BP, indicating that BTBT between the heterojunction of a trilayer−bulk BP is the key to achieving a subthermionic SS. Our work demonstrates the utility of BP heterojunctions in developing energy-efficient switches.