The power-gating (PG) ability of the authors' previously proposed nonvolatile delay flip-flop (NV-DFF) using pseudo-spin-transistors with spin transfer torque magnetic tunnel junctions (STT-MTJs) is computationally analysed. Break-even time (BET) for nonvolatile logic circuits, which is an important index of energy performance for PG systems, is also formulated for the first time. The BET of the proposed NV-DFF can be effectively reduced by the design of the pseudo-spin-transistor parts of the cell. The NV-DFF is applicable to coarse-and fine-grained PG architectures owing to its potential BET of sub-microseconds in practical CMOS logic applications.Introduction: Nonvolatile flip-flops (NV-FFs) have received considerable attention, since they are expected to play an important role for power-gating (PG) systems [1] that dramatically reduce static power dissipation in CMOS logic systems. Recently, we proposed a new nonvolatile delay flip-flop (NV-DFF) using spin-transistor architecture with spin-transfer-torque magnetic tunnel junctions (STT-MTJs) [2]. In the work reported in this Letter, we evaluated the ability of the proposed NV-DFF for PG and developed a power aware design technique of the NV-DFF for reducing its break-even time (BET) [3].
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