Nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs for power-gating systems

Abstract

The power-gating (PG) ability of the authors' previously proposed nonvolatile delay flip-flop (NV-DFF) using pseudo-spin-transistors with spin transfer torque magnetic tunnel junctions (STT-MTJs) is computationally analysed. Break-even time (BET) for nonvolatile logic circuits, which is an important index of energy performance for PG systems, is also formulated for the first time. The BET of the proposed NV-DFF can be effectively reduced by the design of the pseudo-spin-transistor parts of the cell. The NV-DFF is applicable to coarse-and fine-grained PG architectures owing to its potential BET of sub-microseconds in practical CMOS logic applications.Introduction: Nonvolatile flip-flops (NV-FFs) have received considerable attention, since they are expected to play an important role for power-gating (PG) systems [1] that dramatically reduce static power dissipation in CMOS logic systems. Recently, we proposed a new nonvolatile delay flip-flop (NV-DFF) using spin-transistor architecture with spin-transfer-torque magnetic tunnel junctions (STT-MTJs) [2]. In the work reported in this Letter, we evaluated the ability of the proposed NV-DFF for PG and developed a power aware design technique of the NV-DFF for reducing its break-even time (BET) [3].

A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure

“…Table II summarizes comparison of a CMOS FF and five MTJ-based NVFFs. While transistor counts of [4] are small, the effective area is large since CMOS inverters in the slave latch must be enlarged to drive sufficient write current, which results in large active power dissipation for the normal operation. The use of external write driver in [1,6] also causes delay and power overheads due to additional gate capacitance of their write drivers.…”

“…While previous works have zero-standby power capability by the use of the power gating technique, their standby power dissipations without the power gating technique are higher than that of the CMOS FF due to their peripheral circuits for store and recall operations. The amounts of the store energy in [4,5,6] are large since write current must be driven via high MTJ Fig. 5.…”

“…In terms of recall energy, [1], [4], [6] consume relatively high recall energy since these NV-FFs utilize differential current sensing and read currents flows through two STT-MTJ/DWM devices simultaneously. Meanwhile, the pro- posed NV-FF exhibits the same degree of standby power dissipation without the power gating technique owing to its simplified circuitry.…”

“…A nonvolatile flip-flop (NV-FF) [1,3,4,5,6] is an essential component for a nonvolatile logic LSI since temporal data of each function block must be clock-synchronized and retained during poweroff. Because temporal data in an NV-FF must be stored in a nonvolatile device every time before power-off, it is very important that the nonvolatile device has unlimited endurance as well as fast switching capability in nanoseconds.…”

“…To perform CMOS compatible high-speed operation, some MTJ-based NV-FFs operate as CMOS D-FFs during the normal operation, and MTJ read/write accesses are performed just only before power-on/off [1,4,5,6]. Fig.…”