A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure

Abstract

A nonvolatile flip-flop (NV-FF) is proposed for a zerostandby-power LSI using a domain-wall motion (DWM) device. Since the write current path is separated from the read current path in the DWM device, two nonvolatile memory function blocks, a write driver for storing temporal data into the DWM device, and a sense amplifier for recalling the stored data from the DWM device can be optimized independently. Moreover, the use of a nonvolatile storage cell with a DWM-device-based single-ended structure makes it possible to implement both of these functions as two CMOS inverters, which makes it possible to merge them into a CMOS delay flip-flop (D-FF) core. Since the nonvolatile storage cell is electrically separated from the D-FF core during the normal operation, there is no performance degradation. In fact, the area and the power-delay product of the proposed NV-FF are minimized compared to those of the previous works.

Magnetic-tunnel-junction based low-energy nonvolatile flip-flop using an area-efficient self-terminated write driver

“…1,2 Because all the temporal data in each function block must be retained during power-off, a nonvolatile flip-flop (NV-FF) is an essential component for nonvolatile logic large scale integrations (LSIs). [3][4][5][6][7] To implement an NV-FF, a nonvolatile storage device must satisfy two requirements: 1 (1) virtually unlimited endurance, because temporal data must be backed up every time before power-off and (2) three-dimensional stacking capability and CMOS compatibility, for area efficiency. From these viewpoints, a magnetic tunnel junction (MTJ) device 8,9 is regarded as the most viable candidate.…”

“…Because only one MTJ device is needed and a part of the CMOS FF core is reused for recalling the stored data, the use of single-ended circuitry makes it possible to reduce the hardware overhead. 7 Moreover, the self-write-termination circuitry is simplified by the use of the symmetrical structure of the write current path. As a result, the smallest write energy as well as power-delay product is achieved compared to other MTJ-based NV-FFs.…”

“…Figure 1(b) shows a schematic diagram of the storage cell used in the proposed NV-FF in which singleended voltage sensing is utilized for reading. 7,17 The stored data are read as voltage signal V R by the voltage division [This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions.…”

Challenge of Nonvolatile Logic LSI Using MTJ-Based Logic-in-Memory Architecture

“…3b, it would be possible to improve the performance of the nonvolatile logic LSI. In the following description, some concrete design examples using MTJ-based nonvolatile NV-LIM architecture such as nonvolatile field programmable gate array (FPGA) [6][7][8][9][10][11][12][13][14], nonvolatile ternary content-addressable memory (TCAM) [15][16][17][18][19][20][21][22], and nonvolatile randomaccess logic-LSI unit (MCU) [23,24] are demonstrated and their usefulness is discussed. Power : greatly reduced, Delay : shorter Field programmable gate array (FPGA) is a key device to quickly realize prototyping systems, where their specification and function are directly programmable by users, while power consumption as well as hardware cost is a serious problem in expanding application fields of FPGAs, especially in the field of mobile and portable applications [25].…”

“…Redundant MTJs NV-LIM architecture [10,11]. As a future prospect, it is also important to design nonvolatile logic LSI using three-terminal MTJ (3T-MTJ) device [12][13][14], because write current path is separated from read current path in the 3T-MTJ device [26,27], which greatly mitigates the circuit-design restricts of nonvolatile logic LSIs. Figure 12 shows a 3-T MTJ-based nonvolatile LE.…”