Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices

Suzuki, Daisuke; Oka, Tetsuo; Hanyu, Takahiro

doi:10.1016/j.mejo.2018.10.013

Cited by 2 publications

(2 citation statements)

References 23 publications

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“…Hspice models were developed to test the functionality of various logic gates. For LUT circuits based on nonvolatile logic-inmemory (NVLIM) in conjunction with MTJ, a circuit optimization method is recommended [22]. There are three important things to consider in the NVLIM-based LUT chain optimization technique.…”

Section: Related Workmentioning

confidence: 99%

An optimal design modeling of non-volatile dynamical reconfigurable FPGA using SOT-MRAM for ultra-low power applications

Hussain¹,

Reddy²,

Kishore³

2022

Preprint

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The rapid development of reconfigurable FPGA circuits will facilitate their use and operation at low cost. The design of internal memory of FPGA circuit controls their future development. Spin RAM and Magnetic RAM (MRAM) are the best solutions for FPGA for reducing power and writing time. In terms of memory technology, MRAM is becoming more and more attractive in the industry due to its promising capabilities. The physical design range still causes significant radiation effects such as write error rate, access time, tunnel breakage, and low MRAM power consumption. However, random MRAM writing processes affect their yield, so process variations should be investigated, which increases the complexity of yield analysis. For further enhancement of non-volatile FPGA circuits, we propose an optimal design modeling of non-volatile dynamical reconfigurable FPGA using SOT-MRAM for ultra-low power applications. We first introduce a spin-orbit torque-based MRAM (SOT-MRAM), which significantly reduces exposure to radiation caused by offline reading and writing. We design SOT-MRAM based on a double barrier magnetic tunnel connector (DMTJ) with two reference layers to ensure high power and right length. After that, we develop an optimal SOT-MRAM design using the butterfly induced sunflower optimization (BSFO) algorithm which optimizes the design parameters of writing processes. Finally, the simulation results of proposed design can be compared with the existing state-of-art designs in terms of different simulation metrics.

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Section: Related Workmentioning

confidence: 99%

An optimal design modeling of non-volatile dynamical reconfigurable FPGA using SOT-MRAM for ultra-low power applications

Hussain¹,

Reddy²,

Kishore³

2022

Preprint

View full text Add to dashboard Cite

show abstract

“…However, the voltage difference is strongly affected by process variation in the conventional NV-LUT circuit because of its active-load-shared structure. Parasitic components such as wire resistance and capacitance of memory cells 30) also affect the performance.…”

Section: Introductionmentioning

confidence: 99%

Design of an active-load-localized single-ended nonvolatile lookup-table circuit for energy-efficient binary-convolutional-neural-network accelerator

Suzuki

Oka

Hanyu

2022

Jpn. J. Appl. Phys.

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A nonvolatile lookup table (NV-LUT) circuit, which is a key component of a field programmable gate array (FPGA), is proposed for an energy-efficient yet high-performance binarized convolutional neural net-work (BCNN) accelerator. Since the active load is distributed to each configuration memory cell, the effect of the parasitic components is greatly reduced. Moreover, the use of a wired-OR logic-circuit style makes it possible to perform a high-speed logic operation. The proposed 6-input NV-LUT circuit using an active-load-localized single-ended circuit style is designed using a 45-nm CMOS technology and the delay is reduced by 30% with only 13% of hardware overhead compared to those of a conventional circuit. It is also demonstrated that the proposed NV-LUT circuit exhibits variation resilience against three process corners. The use of the proposed NV-LUT circuit also makes it possible to reduce 47% of energy consumption of a BCNN accelerator for digit recognition.

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Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices

Cited by 2 publications

References 23 publications

An optimal design modeling of non-volatile dynamical reconfigurable FPGA using SOT-MRAM for ultra-low power applications

An optimal design modeling of non-volatile dynamical reconfigurable FPGA using SOT-MRAM for ultra-low power applications

Design of an active-load-localized single-ended nonvolatile lookup-table circuit for energy-efficient binary-convolutional-neural-network accelerator

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