Monolithic integration of pseudo-spin-MOSFETs using a custom CMOS chip fabricated through multi-project wafer service

Yamamoto

2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

2014

0.5V operation and power-gating ability of nonvolatile SRAM (NV-SRAM) cell using pseudo-spin-FinFETs (PS-FinFETs) are investigated. The cell is configured so as to achieve a minimum occupied-area design, i.e., all the FinFETs used in the cell are designed with a single fin channel. The 0.5V operations are analyzed from various static noise margins (SNMs) for the normal operation and nonvolatile power-gating (NVPG) modes. The SNMs for all the normal (hold, read, and write) operations are satisfactorily large even for the 0.5V operation, although the wordline underdrive technique is needed to be introduced for the read operation. The SNMs for the store operations of the NVPG mode also satisfy requirements for the shutdown and wake-up operations, when bias-assisted techniques are employed for the PS-FinFETs of the cell. Energy performance of the NV-SRAM cell is evaluated using break-even time (BET). A sufficiently short BET applicable to fine-grained NVPG of microprocessors and SoCs can be achieved even for the 0.5V operation with the various bias-assisted techniques. In addition, store-free shutdown architecture is further effective at reducing BET. Average power of the cell can be dramatically reduced by 0.5V operation, although the reduction rate depends on the leakage current during shutdown mode and the proportion of shutdown period. This FinFET-based NV-SRAM cell using pseudo-spin-transistor architecture is promising for NVPG of low-voltage logic systems.

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Section: Introductionmentioning

confidence: 89%

0.5V operation and performance of nonvolatile SRAM cell based on pseudo-spin-FinFET architecture

Yamamoto

2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

2014

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“…The maximum g MC value was as high as 45 %. The CIMS behavior in a PS-MOSFET and monolithic integration of PS-MOSFETs using a vendor-made CMOS chip were also investigated [83,84].…”

Section: Pseudo-spin-mosfet Technologymentioning

confidence: 99%

Devices and Applications: Spin Transistors and Spin Logic Devices

Takamura

Handbook of Spintronics

et al. 2014

In this chapter, field-effect spin transistors are described from the viewpoint of integrated circuit applications. Firstly, the classification of field-effect spin transistors is described. Then, the MOSFET type of spin transistor, i.e., spin-MOSFET, is focused on, and its device structure, operating principle, performance, and device/process technologies are shown. Pseudo-spin-MOSFET architecture that is a circuit technique for reproducing the functions of spin transistors using an ordinary MOSFET and a magnetic tunnel junction is also described. Finally, technologies, advantages, and issues for energy-efficient logic circuits/systems based on these spin-functional MOSFETs are also addressed.

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Spin‐Transistor Technology for Spintronics/CMOS Hybrid Logic Circuits and Systems

Nanomagnetic and Spintronic Devices for Energy‐Efficient Memory and Computing

Yamamoto

2016