1.5 nm equivalent thickness Ta/sub 2/O/sub 5/ high-k dielectric with rugged Si suited for mass production of high density DRAMs

Asano, Ichiro; Kunitomo, M.; Yamamoto, S.; Furukawa, R.; Sugawara, Yutaka; Uemura, T.; Kuroda, Jun; Kanai, Masaki; Nakata, M; Tamaru, T.; Nakamura, Yoshitaka; Kawagoe, Takeshi; Yamada, Shohei; Kawakita, K.; Kawamura, Hiroaki; Nakamura, M.; Morino, Mario; Kisu, T.; Iijima, S.; Ohji, Y.; Sekiguchi, T.; Tadaki, Yoshitaka

doi:10.1109/iedm.1998.746466

Cited by 4 publications

(4 citation statements)

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“…Capacitors of this type have a metal-insulator-semiconductor ͑MIS͒ structure, so the Ta 2 O 5 is formed on a polysilicon electrode. 1 In the fabrication of MIS capacitor, silicon dioxide, which has a low dielectric constant, is grown at the interface between Ta 2 O 5 and the polysilicon electrode. This interfacial layer reduces the effective capacitance.…”

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confidence: 99%

Combining Ta[sub 2]O[sub 5] and Nb[sub 2]O[sub 5] in Bilayered Structures and Solid Solutions for Use in MIM Capacitors

Matsui

Hiratani

Kimura

et al. 2005

J. Electrochem. Soc.

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Binary systems of Ta 2 O 5 and Nb 2 O 5 are investigated as dielectric materials that allow low-temperature fabrication and are suitable for use in metal-insulator-metal ͑MIM͒ capacitors. This investigation shows that a Nb 2 O 5 film is crystallized in a hexagonal symmetry at a temperature of less than 500°C, which is more than 250°C lower than the corresponding temperature for a Ta 2 O 5 film. Using Nb 2 O 5 as a nucleation layer lowers the crystallization temperature for Ta 2 O 5 to less than 500°C. This is because hexagonal Ta 2 O 5 is stably formed on the hexagonal Nb 2 O 5 by heteroepitaxy. A Ta 2 O 5 /Nb 2 O 5 bilayer with a high dielectric constant of 50 can therefore be prepared by a 500°C fabrication process. Solid solutions of Nb 2 O 5 and Ta 2 O 5 are also investigated. The substitution of 10% Nb 2 O 5 in Ta 2 O 5 to form ͑Ta 0.9 Nb 0.1 ͒ 2 O 5 was found to decrease the temperature of crystallization from 700°C for pure Ta 2 O 5 to 550°C. The dielectric constant of the ͑Ta 0.9 Nb 0.1 ͒ 2 O 5 film is approximately 20% greater than that of the Ta 2 O 5 film. This is because the substitutional Nb 2 O 5 stabilizes the material in the hexagonal phase, which corresponds to a high dielectric constant, at lower temperatures.

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confidence: 99%

Combining Ta[sub 2]O[sub 5] and Nb[sub 2]O[sub 5] in Bilayered Structures and Solid Solutions for Use in MIM Capacitors

Matsui

Hiratani

Kimura

et al. 2005

J. Electrochem. Soc.

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“…With increasing miniaturization, it is increasingly difficult to ensure the storage capacitance (Cs) of DRAM (Dynamic Random Access Memory). Capacitance insulation films with a large relative permittivity such as tantalum pentoxide (Ta 2 O 5 ) [1], strontium titanium oxide [(Sr, Ti)O 3 ] [2], and barium strontium titanium oxide [(Ba, Sr)TiO 3 ] [3] have been studied. In particular, after the generation with a minimum processing dimension (F) of 0.10 µm, it is considered necessary to use a lower electrode measuring more than 3 µm (for the concave type) in order to ensure the necessary Cs (25 fF/bit), even if the MIS (metal insulator silicon)/Ta 2 O 5 capacitor presently in use [1] is employed (see Fig.…”

Section: Introductionmentioning

confidence: 99%

Development of MIM/Ta₂O₅ capacitor process for 0.10‐µm DRAM

Asano¹,

Nakamura²,

Hiratani

et al. 2004

Electron Comm Jpn Pt II

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SUMMARYAs the fabrication dimension becomes smaller, it becomes increasingly difficult to ensure storage capacitance for DRAM. For this reason, a capacitor process using high-permittivity insulating films is strongly desired. In the research reported here, an MIM/tantalum pentoxide capacitor process is developed with ruthenium as an electrode material. The ruthenium CVD technique, the use of amorphous tantalum nitride as anti-oxide barrier metal, and a contamination elimination process using periodic acid have been developed. By packaging as 0.13-µm DRAM, capacitance performance equivalent to silica film is realized with a film thickness of 0.8 nm. The process is considered to be applicable to 0.10-µm DRAM.

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“…[1][2][3] Therefore, the fabrication of the sub-0.1 m MOSFET devices requires the development of new gate dielectric materials with lower leakage current levels than SiO 2 at the same equivalent oxide thickness values. Alternative dielectric materials, such as Si 3 N 4 , Si 3 N 4 /SiO 2 stack, 4-8 Y 2 O 3 , 9 Al 2 O 3 , 10 TiO 2 , 11,12 Ta 2 O 5 , [13][14][15][16] SrTiO 3 , and (Ba x Sr 1Ϫx )TiO 3 17,18 have been suggested as candidate materials. These materials, however, have demonstrated issues of low dielectric constant values or poor thermal stability with Si substrates.…”

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confidence: 99%

“…These materials, however, have demonstrated issues of low dielectric constant values or poor thermal stability with Si substrates. [11][12][13][14][15][16][17][18] Recently, ZrO 2 , [19][20][21] HfO 2 , 22,23 and their silicates 24,25 have been considered as promising alternative gate dielectric materials due to their high dielectric constant values and good thermal stabilities with Si substrates. 26 Among the key issues related to the high-k gate stack such as gate poly depletion effects or boron penetration, 27 is interfacial instability in direct contact with gate electrode materials as well as with Si substrates.…”

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confidence: 99%

Characteristics of ZrO[sub 2] Films with Al and Pt Gate Electrodes

Nam

Yoo

Nam

et al. 2003

J. Electrochem. Soc.

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We investigated interfacial stabilities of ZrO 2 films with Al and Pt electrodes formed by magnetron sputtering upon annealing and consequent changes of their metal-oxide-semiconductor capacitor characteristics. The as-deposited ZrO 2 films deposited using a sputtering power of 300 W were amorphous, while after annealing in N 2 at 600°C for 5 min the films became polycrystalline with a mixture of monoclinic and tetragonal phases. After the deposition of electrodes, we found that the amorphous interlayer which is presumed to be Al 2 O 3 was formed at the ZrO 2 /Al interface, while platinum ͑Pt͒ electrodes showed no interlayer at the interface with ZrO 2 films. The value of the capacitance equivalent thickness for the ZrO 2 film with the Al electrode was larger than that of the case with the Pt electrode by about 12 Å, which is due to the presence of the additional Al 2 O 3 interlayer at the Al/ZrO 2 interface. The capacitance-voltage measurement showed that the difference in flatband voltage (V FB ) between the ZrO 2 films and the two different electrodes is about 1.2 V, which is due to the work function difference between the two electrode materials.

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1.5 nm equivalent thickness Ta/sub 2/O/sub 5/ high-k dielectric with rugged Si suited for mass production of high density DRAMs

Cited by 4 publications

References 0 publications

Combining Ta[sub 2]O[sub 5] and Nb[sub 2]O[sub 5] in Bilayered Structures and Solid Solutions for Use in MIM Capacitors

Combining Ta[sub 2]O[sub 5] and Nb[sub 2]O[sub 5] in Bilayered Structures and Solid Solutions for Use in MIM Capacitors

Development of MIM/Ta₂O₅ capacitor process for 0.10‐µm DRAM

Characteristics of ZrO[sub 2] Films with Al and Pt Gate Electrodes

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1.5 nm equivalent thickness Ta/sub 2/O/sub 5/ high-k dielectric with rugged Si suited for mass production of high density DRAMs

Cited by 4 publications

References 0 publications

Combining Ta[sub 2]O[sub 5] and Nb[sub 2]O[sub 5] in Bilayered Structures and Solid Solutions for Use in MIM Capacitors

Combining Ta[sub 2]O[sub 5] and Nb[sub 2]O[sub 5] in Bilayered Structures and Solid Solutions for Use in MIM Capacitors

Development of MIM/Ta2O5 capacitor process for 0.10‐µm DRAM

Characteristics of ZrO[sub 2] Films with Al and Pt Gate Electrodes

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Development of MIM/Ta₂O₅ capacitor process for 0.10‐µm DRAM