A tantalum–pentoxide dielectric with an enhanced permittivity of over 50 was found to be crystallized in a hexagonal symmetry with a=0.628 nm and c=0.389 nm. The incommensurate epitaxy of tantalum pentoxide on hcp-ruthenium metal stabilizes the hexagonal phase with √3-time periodicity in plane, as compared with that of the known hexagonal δ phase. The crystallographic assumption, which is based on one-dimensional Ta–O–Ta chain along the c axis, can explain large polarizability caused by delocalized electrons on the one-dimensional chain.
The effects of post-deposition annealing on the microstructure of tantalum oxide ( Ta2O5) deposited on Si are evaluated by means of X-ray photoelectron spectroscopy. With the peak decomposition technique and the angle-resolved X-ray photoelectron spectroscopy (ARXPS) method we found that there is SiO2 layer and Ta suboxide at the interface. By using a simple two-layer model, the thickness of both the Ta2O5 layer and the interfacial SiO2 layer could be evaluated. Investigating Ta2O5 films this way before and after annealing revealed that annealing has the following effects on the interfacial reaction. With post-deposition annealing under O2, Ar, or N2 gas, the Si substrate is oxidized by oxygen from the Ta2O5 layer. The Ta2O5 is partly reduced and N2 gas activates this reaction. The thickness of the interfacial SiO2 layer is reduced by nitridation of the Si substrate.
We demonstrate a novel MIM capacitor with a heteroepitaxial Ta20s dielectric, the permittivity of which is as high as 50. The heteroepitaxy of Ta20s on the Ru electrode changes its crystal symmetry from a conventional orthorhombic system to a hexagonal one. One-dimensional Ta-0-Ta chains along the c-axis bring about delocalized electrons, large polarizability and thus enhanced permittivity. This technology is promising for the application of Ta20s to the G-bit DRAMs, eliminating the need to use such exotic materials as BST and STO.
Kokubunji, Tokyo 185 ,Japan s t r u c t u r e i s also discussed.A new device structure GOLD (gate-drain overlapped LDD) i s proposed to achieve high reliability and h i g h performance i n deep submicron MOSFETs. T h i s device takes advantage of the gate-drain overlap effect. The GOLD device concept i s d i f f e r e n t from t h a t of drain-engineering methods such a s the double diffused drain (DDD) and l i g h t l y doped drain (LDD). GOLD eliminates the tradeoff betveen transconductance and breakdovn voltage (hot-carrier, drain sustaining). The "overlap effect" of GOLD devices i s discussed u s i n g device simulation and experimentation. I n t h e fabrication process, GOLD has a novel gate structure using a natural oxide film (5-10 A ) t o o b t a i n the overlapped fine structure. The GOLD process i s a l s o compatible v i t h conventional LDD processes. A s a r e s u l t , GOLD will be s u i t a b l e f o r 0.5-0.3 pm design rule devices at 5 V operation, not 3 V. 8 1. INTRODUCTION Y i t h device dimensions scaled dovn t o under 0.5pm, the inevitable problems such a s reduced r e l i a b i l i t y and lowered punch-through voltage require that power s u p p l y voltage be reviewed and/or device structure rebuilt. Certainly, i t i s d e s i r a b l e , i f highly reliable device operation i s p o s s i b l e a t 5 V s u p p l y voltage. The "drain-engineering" methods such a s the double diffused drain (DDD) and l i g h t l y doped drain (LDD) have so f a r been used t o achieve high r e l i a b i l i t y , However, even i f t h e s e d r a i n s t r u c t u r e s are applied, 5 V operation seems impossible, and the tradeoff betveen transconductance and device breakdovn voltage (hot-carrier, drain sustaining) indeed exists i n these devices.These problems can be solved by optimizing n o t only n-length L n and n-dose Yd but also gate-drain/source overlap l e n g t h r. This paper proposes a new device concept vhich takes advantage of the gate-drain overlap effect[l][Z] 131 t o improve r e l i a b i l i t y , performance, and punchthrough c h a r a c t e r i s t i c s . From t h i s concept, a novel submicron device GOLD (gate-drain overlapped LDD) i s proposed. GOLD has a 2-3 V higher drain sustaining voltage than conventional LDDs. A new method t o precisely fabricate the GOLD 5 2 . DEVICE FABRICATION A schematic cross section of GOLD i s shown i n Fig. 1. The s t r u c t u r e c o n s i s t s of tvo main parts: 6 a double-layer gate w i t h a thin etch-stop intermediate layer, and 0 SELOCS[41 (selective oxide coating of silicon-gate) sidevalls to control the overlap length I?. The GOLD process i s shown i n Fig. 2. The process flow u p to gate oxidation i s conventional. A natural oxide film (5-10 A ) i s grown by air-curing wafer a f t e r d e p o s i t i n g t h e f i r s t p o l y s i l i c o n l a y e r of 50 nm thickness. The second polysilicon layer and a CVD oxide layer (HLD (1)) are then deposited on the natural oxide ( Fig. ?.(a)). In this GOLD process, gate etching i s t h e key process. Th...
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