Low-temperature electron-cyclotron-resonance microwave plasma etching and reactive ion etching are described for ULSI device fabrication. Highly selective anisotropic etching at a high rate, which implies dry etching without tradeoffs, is performed without changing the discharge parameters. This etching is only achieved at reduced wafer temperatures. The etching mechanism and the model are discussed based on the etching yield results obtained by the mass-selected reactive ion beam etching experiments. The new etching system and the etching properties obtained for the low-temperature etching are reviewed comparing those obtained in the conventional reactive ion etching and electron-cyclotron-resonance microwave plasma etching.

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A superconducting field-effect transistor (FET) with a 0.1pm-length gate electrode was fabricated and tested at liquid-helium temperature. Two superconducting electrodes (source and drain) were formed on the same Si substrate surface with an oxide-insulated gate electrode by a self-aligned fabrication process. Superconducting current flowing through the semiconductor (Si) between the two superconducting electrodes (Nb) was controlled by a gate-bias voltage.superconducting device with three terminals using dc A power is desired for development of superconducting integrated circuits. Several types of three-terminal superconducting devices have been proposed and experimentally tested [ 11-[5]. Superconducting field-effect transistors (FET's) have excellent input/output isolation compared with others. The first experimental superconducting FET was realized by the authors [6]. The gate electrode was formed on the opposite side of the Si single-crystal film from the two superconducting electrodes, so these devices were not suitable for integrated circuits. Takayanagi and Kawakami [7] and Ivanov et al. [8],[9] reported on superconducting FET's using compound semiconductors. The gate lengths of their devices were about 0.5 and 0.4 pm, respectively, much larger than that of shortchannel Si MOSFET's. A smaller gate length is necessary to improve the switching speed of the superconducting FET's and to realize highly integrated circuits, because a small gatelength superconducting FET has a larger superconducting current to drive the next stage. However, planar devices with a short gate length have been difficult to fabricate on one side of a Si single crystal because the two superconducting electrodes are less than 0.2 pm apart in a Si semiconductor substrate and the gate electrodes must lie between the two.In this paper we describe the fabrication and operation of a superconducting FET with a gate length as short as 0.1 pm. This FET has a planar structure with a gate electrode between the two superconducting electrodes on the same side of a Si single crystal. The electric characteristics are measured at 4.2 K and the static characteristics are discussed.A cross-sectional view is shown in Fig. 1. The device has a single-crystal Si substrate, two As+ ion-implanted areas, a gate oxide, a poly-Si gate electrode, and a superconducting source and drain. The original aspect of this structure is the 0.1 -pm-length gate electrode with an overhang and insulating sidewalls of very thin Si3N4 film. A top view of the device and a scanning-electron micrograph of the gate structure are shown in Fig. 2(a) and (b), respectively. Fig. 1. Cross-sectional view of the superconducting FET with 0.1-pm gate \ , / Sdurce electrode(Nb1 Drain electrode(Nb) (a) -150nm (b) scanning electron micrograph of the gate structure (cross-sectional view).Fig. 2. (a) Micrograph of the superconducting FET (top view) and (b)A multilayer of gate oxide, doped poly-Si, and Si3N4 was formed on a surface of the p-Si single-crystal substrate. The gate oxide was a therma...

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