This study examined the impacts of hemlock woolly adelgid (Adelges tsugae Annand) (HWA), a small, invasive insect, on foliar chemistry, forest floor microclimate, and subsequent green foliage decomposition in eastern hemlock (Tsuga canadensis (L.) Carrière) forests. We investigated the direct effects of HWA feeding and indirect changes in microclimate on foliar decomposition by incubating HWA-infested and uninfested foliage across eight eastern hemlock dominated stands in southern New England that had different histories of HWA infestation. Infested stands had much poorer average crown health (3.4 versus 1.4 crown loss ratings), higher percent open sky (10.9 ± 2.4 vs. 5.3 ± 0.5 gap light index), and lower organic soil moisture (0.83 ± 0.02 g·g -1 vs. 1.06 ± 0.05 g·g -1 ) than uninfested stands. There were no significant differences in percent C, percent N, or percent lignin for the excised foliage at the start of the study. However, after 120 days, decomposing foliage from infested trees had significantly higher N concentrations (1.83% ± 0.05% vs. 1.69% ± 0.02 %) and lower C/N ratios (29.9 ± 0.8 vs. 31.6 ± 0.2) than uninfested foliage, suggesting that HWA herbivory resulted in alterations of litter chemistry as decomposition progressed. Mass loss of common uninfested foliage was lower in uninfested hemlock stands than in infested ones (30.9% ± 0.7% vs. 34.2% ± 0.1%). These rates of mass loss were significantly correlated with microclimate factors and indicate that organic soil moisture levels are controlling decomposition in HWA-infested forests. Infestation by HWA causes virtually no direct feeding damage to foliage, but it does lead to several indirect and significant ecological and functional changes over the 10-to 20-year course of infestation and stand decline.Résumé : Cette étude examine les impacts du puceron lanigère de la pruche (Adelges tsugae Ann.), un petit insecte invasif, sur les propriétés chimiques du feuillage, le microclimat dans la couverture morte et la décomposition subsé-quente du feuillage vert dans les forêts de pruche du Canada (Tsuga canadensis (L.) Carrière). Nous avons étudié les effets directs du puceron lanigère de la pruche et les changements indirects du microclimat sur la décomposition du feuillage en incubant du feuillage sain et du feuillage infesté par le puceron lanigère de la pruche dans huit peuplements dominés par la pruche du Canada dans le sud de la Nouvelle-Angleterre qui avaient différents historiques d'infestation par le puceron lanigère de la pruche. Les peuplements infestés étaient caractérisés par un état de santé des cimes beaucoup plus détérioré (3,4 vs. 1,4 d'indice de perte de cime), un pourcentage plus élevé d'ouverture du couvert (10,9 ± 2,4 vs. 5,3 ± 0,5 de coefficient de trouées lumineuses) et une humidité du sol organique plus faible (0,83 ± 0,02 vs. 1,06 ± 0,05 g·g -1 ) que les peuplements sains. Il n'y avait pas de différence significative dans le pourcentage de C, N ou de lignine du feuillage excisé au début de l'étude mais, après 120 jours, le feuillage...

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Abstract-A new circuit-level single-event upset (SEU) hardening approach for high-speed SiGe HBT current-steering digital logic is introduced and analyzed using both device and circuit simulations. The workhorse D-type flip-flop circuit architecture is modified in order to significantly improve its SEU immunity. Partial elimination of the effect of cross-coupling at the transistor level in the storage cell of this new circuit decreases its vulnerability to SEU. The SEU response of this new circuit is quantitatively compared with three other D flip-flop architectures, including the unhardened circuit, a conventional NAND gate based circuit, and a current-sharing hardened (CSH) circuit, at both variable data rate and switching current. The new circuit shows substantial improvement in SEU response over the unhardened version, with little increase in layout complexity and power consumption. While the NAND gate based circuit still shows better SEU response than the other circuits, its high power consumption will preclude its use in space applications. Our results suggest that this new circuit architecture exhibits sufficient SEU tolerance, low layout complexity, and modest power consumption, and thus should prove suitable for many space applications requiring very high-speed digital logic.

We compare heavy ion and proton SEE data on commercial SiGe technologies from IBMs 7 HP and 5 AM processes and Jazz Semiconductors SiGe120 process at data rates from 50 Mb/s to 12.4 Gb/s. Complex burst-error trends correlate with both data rate and particle LET, as well as pulsed laser probing of both data paths and clock distribution circuitry.Index Terms-Ground testing, high-speed testing, silicon germanium (SiGe), single-event effect (SEE), single-event upset (SEU).

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We present, for the first time, an analysis of the error signatures captured during pulsed laser microprobe testing of high-speed digital SiGe logic circuits. 127-bit shift registers, configured using various circuit level latch hardening schemes and incorporated into the circuit for radiation effects self test serve as the primary test vehicle. Our results indicate significant variations in the observed upset rate as a function of strike location and latch architecture. Error information gathered on the sensitive transistor nodes within the latches and characteristic upset durations agree well with recently reported heavy-ion microprobe data. These results support the growing credibility in using pulsed laser testing as a lower-cost alternative to heavy-ion microprobe analysis of sensitive device and circuit nodes, as well as demonstrate the efficiency of the autonomous detection and error approach for high speed bit-error rate testing. Implications for SEU hardening in SiGe are addressed and circuit-level and device-level Radiation Hardening By Design recommendations are made.Index Terms-Built-in self-test, circuit level hardening, highspeed bit-error rate testing, pulsed laser testing, silicon-germanium (SiGe), single-event effects (SEU).

We present measurements of proton induced degradation in emerging low power high performance InAs based devices, including InAs/AlSb high electron mobility transistors (HEMT) and In0.86Ga0.14As base 6.0 A lattice constant double heterojunction bipolar transistor (DHBT) devices.