SEU Error Signature Analysis of Gbit/s SiGe Logic Circuits Using a Pulsed Laser Microprobe

Abstract

We present, for the first time, an analysis of the error signatures captured during pulsed laser microprobe testing of high-speed digital SiGe logic circuits. 127-bit shift registers, configured using various circuit level latch hardening schemes and incorporated into the circuit for radiation effects self test serve as the primary test vehicle. Our results indicate significant variations in the observed upset rate as a function of strike location and latch architecture. Error information gathered on the sensitive transistor nodes within the latches and characteristic upset durations agree well with recently reported heavy-ion microprobe data. These results support the growing credibility in using pulsed laser testing as a lower-cost alternative to heavy-ion microprobe analysis of sensitive device and circuit nodes, as well as demonstrate the efficiency of the autonomous detection and error approach for high speed bit-error rate testing. Implications for SEU hardening in SiGe are addressed and circuit-level and device-level Radiation Hardening By Design recommendations are made.Index Terms-Built-in self-test, circuit level hardening, highspeed bit-error rate testing, pulsed laser testing, silicon-germanium (SiGe), single-event effects (SEU).

Single-event response of the SiGe HBT in TCAD simulations and laser microbeam experiment

“…SEE simulation with laser microbeam is a simple and convenient method in SEE studies because it can focus into a small beam size and is capable of scanning sensitive junctions of devices. [17][18][19] The SiGe HBT under test is loaded with a collector resistance of 50 Ω, and the wavelength of the laser microbeam is 1064 nm with a laser spot size of approximately 1.6 µm in diameter. In order to access the device within sensitive regions, the laser spot must focus on the opening top metal layers in front of the device.…”

Design and verification for CDC synchronization based on TMR

“…To verify the CDC synchronizers based on TMR, metastability and SEUs should both be taken into consideration. However, because the event that metastability and SEUs happen simultaneously is rare in practical projects, traditional methods for detecting metastability and SEUs are time-consuming and costly [31]. Moreover, if the problems are found after the design tape out, designers need redesign and tape out chips again.…”