An SEU hardening approach for high-speed SiGe HBT digital logic

Abstract

Abstract-A new circuit-level single-event upset (SEU) hardening approach for high-speed SiGe HBT current-steering digital logic is introduced and analyzed using both device and circuit simulations. The workhorse D-type flip-flop circuit architecture is modified in order to significantly improve its SEU immunity. Partial elimination of the effect of cross-coupling at the transistor level in the storage cell of this new circuit decreases its vulnerability to SEU. The SEU response of this new circuit is quantitatively compared with three other D flip-flop architectures, including the unhardened circuit, a conventional NAND gate based circuit, and a current-sharing hardened (CSH) circuit, at both variable data rate and switching current. The new circuit shows substantial improvement in SEU response over the unhardened version, with little increase in layout complexity and power consumption. While the NAND gate based circuit still shows better SEU response than the other circuits, its high power consumption will preclude its use in space applications. Our results suggest that this new circuit architecture exhibits sufficient SEU tolerance, low layout complexity, and modest power consumption, and thus should prove suitable for many space applications requiring very high-speed digital logic.

Heavy-ion broad-beam and microprobe studies of single-event upsets in 0.20-/spl mu/m SiGe heterojunction bipolar transistors and circuits

“…Previous investigations have examined SEE response of 5HP HBT circuits through both circuit testing [3] and modeling [4]- [6]. Charge collection modeling [7], [8] and measurement [8] studies in the 5HP process have also been conducted, but to date no measurements have been reported on charge collection or circuit response in 7HP SiGe HBT structures.…”

Hardware Considerations for Spectral Encoded UWB Transmitters

“…However, high speed memory cells with 1750 bits are challenging to design, as the currently reported read speed for a 1024-bit memory is roughly 3GHz [20].…”

Influence of alloy inhomogeneities on the determination by Raman scattering of composition and strain in Si1–xGex/Si(001) layers

“…Larger carrier mobilities, 1,2 higher device-switching speeds, [3][4][5] and lower power consumption 6 are some of the advantages that make strained SiGe/Si structures a good alternative to their already well established counterpart. Successful inclusion of Ge in a great variety of device architectures such as heterojunction bipolar transistors [7][8][9] (HBTs), metal-oxide-semiconductor field-effect transistors [10][11][12] (MOSFETs), and optical modulators 13,14 has been already clearly demonstrated.…”