Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 μm bulk CMOS

J Sign Process Syst Sign Image Video Technol

2007

This paper provides a personal perspective on developments in the implementation of two systolic fast Fourier transform processors over the last 25 years and identifies some of the lessons learned. This has been a period of tremendous advancements in integrated circuit technology that is demonstrated by the resulting processors. The first processor is the Modular Transform Processor that was developed at TRW in the 1982-1984 time frame using VLSI technology. It is a set of six large circuit boards that computes 4,096-point fast Fourier transforms using 22-bit floating-point arithmetic at sustained data rates of 40 MSPS. The second processor is a single ASIC chip systolic FFT processor developed by the Mayo Foundation in the 2001-2002 time frame that computes 4,096-point FFTs using 16-bit fixed-point arithmetic at sustained data rates of 200 MSPS. Some thoughts on the future directions of systolic FFT processor development are offered. Future systems will compute large transforms (e.g., 16 K-point to 1 M-point) at high data rates (e.g., 500 MSPS to 1 GSPS), will employ more precise arithmetic (e.g., 32-bit single precision IEEE Standard floating-point arithmetic), will consume very low power (e.g., on the order of one watt) and will be realized on a single chip.

Section: Discussionmentioning

confidence: 99%

Section: The Asic Systolic Fft Processormentioning

confidence: 99%

Systolic FFT Processors: A Personal Perspective

J Sign Process Syst Sign Image Video Technol

2007

“…An alternative "split pipeline" approach [15] shown on Figure 3 B divides the pipeline into two 256 point pipelines with a reordering unit between the two pipelines. The center reordering unit uses circular buffers implemented with RAM to reorder the data.…”

Section: Soc Implementationmentioning

confidence: 99%

Three dimensional system on chip technology

Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)

2005

Self Cite

With ever-finer device geometry, increasing device counts and interconnect delays playing a larger role in the performance of a system on a chip, the architectures that are used to support such technologies must take these factors into account. Highly pipelined or highly parallel architectures that utilize local processing, and therefore shorter interconnects, are required.Three-dimensional, monolithic integrated circuit technology which can significantly shorten the interconnects and accommodate more devices per chip may be an attractive solution. The basic idea is presented along with an illustrative application specific processor design.

“…Groginsky and Works developed an early pipeline FFT design [11]. Several pipeline FFTs have been implemented [12]- [14]. Later, several pipeline architectures were proposed and designed [15]- [17].…”

Section: Existing Pipeline Fft Architecturesmentioning

confidence: 99%

The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm

Mohd¹,

VLSI-SoC: Advanced Topics on Systems on a Chip

Aziz³

2009

Abstract. This chapter examines the superscalar pipeline Fast Fourier Transform algorithm and architecture. The algorithm presents a memory management scheme that avoids memory contention throughout the pipeline stages. The fundamental algorithm, a switch-based FFT pipeline architecture and an example 64-point FFT implementation are presented. The pipeline consists of log 2 N stages, where N is number of FFT points. Each stage can have M Processing Elements (PEs.) As a result, the architecture speed up is M*log 2 N. The pipeline algorithm is configurable to any M > 1.