Analysis of electrical and scanning transmission electron microscopy (STEM) and electron energy loss spectra (EELS) data suggests that Hf-based high-k dielectrics deposited on a SiO 2 layer modifies the oxygen content of the latter resulting in reduction of the oxide energy band gap and correspondingly increasing its k value. High-k deposition on thinner SiO 2 films, below 1.1 nm, may lead to the formation of a highly oxygen deficient amorphous interfacial layer adjacent to the Si substrate. This layer was identified as an important factor contributing to mobility degradation in high-k transistors.

We report the process module development results and device characteristics of dual metal gate CMOS with TaSiN and Ru gate electrodes on HfO 2 gate dielectric. The wet etch of TaSiN had a minimal impact on HfO 2 (∆EOT<1Å). A plasma etch process has been developed to etch Ru/TaN/Poly (PMOS) and TaSiN/Ru/TaN/Poly (NMOS) gate stacks simultaneously. Well behaved dual metal gate CMOS transistors have been demonstrated with L g down to 85nm.

International SEMATECH, 7BM assignee, bu. of Texas at Austin, ?ntel assignee 2706 Montopolis drive, Austin, TX 78741, USA, Tel) 1-512-356-3115, Fax) 1-512-356-3640, byoung.hnn.lee@sematech.org Abstract Hot carrier reliability of poly-gated and TiN-gated MOSFETs with HfSiON gate dielectric is studied. For short channel devices, worse degradation of HfSiON occurs at v,=vd while oxide devices are degraded more at V,=Vd2 similar to oxide control devices. Localized transient charging at the drain comer of the HfSiON layer is proposed to explain the channel length dependence and time dependent relaxation of HC reliability characteristics.

We have demonstrated a uniform, robust interface for high-k deposition with significant improvements in device electrical performance compared to conventional surface preparation techniques. The interface was a thin thermal oxide that was grown and then etched back in a controlled manner to the desired thickness. Utilizing this approach, an equivalent oxide thickness (EOT) as low as 0.87 nm has been demonstrated on high-k gate stacks having improved electrical characteristics as compared to more conventionally prepared starting surfaces.

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