Localized transient charging and it's implication on the hot carrier reliability of HfSiON MOSFETs

Self Cite

To understand the intrinsic effect of a hot-carrier injection on high-κ dielectrics free from concurrent cold-carrier trapping, the authors have investigated a hot-carrier-induced damage with channel hot-carrier stresses and substrate hotcarrier stress. Compared to substrate hot-carrier stress, the channel hot-carrier stress shows a more significant cold-carrierinjection effect. By using a detrapping bias, they were able to decouple the effect of cold-carrier trapping from the permanent trap generation induced by the hot-carrier injection. As channel hot-carrier stress bias was reduced, a portion of cold-carrier trapping increased and a portion of interface trap generation decreased.

Section: Resultssupporting

confidence: 90%

Section: Introductionmentioning

confidence: 99%

Decoupling of cold-carrier effects in hot-carrier reliability assessment of HfO/sub 2/ gated nMOSFETs

Park

Choi²,

Lee

et al. 2006

Self Cite

“…injected HCs, whereas the cold carriers associated with PBTI have a simultaneous effect on the channel region due to preexisting traps [14], [15]. For this reason, we also expected HCI to exhibit more severe degradation as the temperature increased, which was also observed in a previous study [16].…”

Section: Resultssupporting

confidence: 59%

PBTI-Associated High-Temperature Hot Carrier Degradation of nMOSFETs With Metal-Gate/High- $k$ Dielectrics

Lee

Kang²,

Yoo

et al. 2008

Due to the increased physical dielectric thickness and reduced gate leakage in metal-gate/high-k devices, degradation caused by channel hot carriers (HCs) becomes more significant than positive bias temperature stress. In an analysis of metal-gate/high-k devices, accelerated channel HCs were found to induce permanent interface damage. Moreover, the overall threshold voltage shifts caused by HC stress were enhanced at higher temperatures, which is due to an association with positive bias temperature instability. Therefore, high-temperature HC stress has emerged as a dominant degradation factor in short-channel nMOSFETs with metal-gate/high-k dielectrics.Index Terms-Hot carrier (HC), metal-gate/high-k dielectrics, positive bias temperature instability (PBTI).

“…3. The worst degradation condition (V g = V d = 1.5 and 2.0 V) was chosen for the high-k MOSFETs [11]. Compared with a control sample, the sample annealed in a F 2 ambient showed less ∆V th and less degradation of ∆g m /g m,max under HCS.…”

Section: Resultsmentioning

confidence: 99%

Effect of $\hbox{F}_{2}$ Postmetallization Annealing on the Electrical and Reliability Characteristics of HfSiO Gate Dielectric

Chang

Park

et al. 2007

The effects of fluorine (F 2 ) annealing on the electrical and reliability characteristics of HfSiO MOSFETs were investigated. Compared with a control sample annealed in conventional forming gas (H 2 /N 2 = 4%/ 96%), additional annealing in a fluorine ambient (F 2 /Ar = 0.3%/ 99.7%) at 400 • C for 20 min improved the electrical characteristics such as lower interface trap density and higher transconductance. In addition, MOSFET samples annealed in a F 2 ambient exhibited less degradation under hot-carrier stress and positive bias temperature stress. These improvements can be explained by fluorine incorporation at the high-k/Si interface, which was confirmed by an X-ray photoelectron spectroscopy analysis.Index Terms-Bias temperature instability, fluorine annealing, high-k, hot-carrier stress (HCS).