Effect of $\hbox{F}_{2}$ Postmetallization Annealing on the Electrical and Reliability Characteristics of HfSiO Gate Dielectric

Chang, Man; Jo, Minseok; Park, Hokyung; Hwang, Hyunsang; Lee, Byoung Hun; Choi, Rino

doi:10.1109/led.2006.887941

Cited by 16 publications

(4 citation statements)

References 12 publications

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“…[15][16][17][18] The reduction of D it for the pre-F is attributed to the effective passivation of Si dangling bonds resulting from Si-F bonding formation. 7 The positive shift of V FB is due to the negative fixed charge induced by incorporated F atoms, in agreement with a previous report. 19 However, we cannot exclude the possibility that D it also contributes to V FB shift.…”

Section: Resultssupporting

confidence: 92%

“…F atom implantation was used in an early study, but implanting F was shown to cause uncontrolled oxide regrowth during the gate-stack process. 6 As an alternative, high-temperature F 2 annealing or UV-assisted F 2 annealing was reported to result in effective incorporation of F. 3,7 More recently, F treatment using highly reactive radicals from CF 4 plasmas was reported on the HfO 2 gate oxide prepared by sputtering. 4,8,9 This method is especially preferable for the F treatment of high-k films prepared by a deposition technique using plasma such as plasma-enhanced atomic layer deposition ͑PE-ALD͒, because F treatment can be carried out in situ inside of the deposition chamber.…”

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confidence: 99%

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Effects of Fluorine Plasma Treatment on the Electronic Structure of Plasma-Enhanced Atomic Layer Deposition HfO[sub 2]

Maeng

Son

2009

J. Electrochem. Soc.

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We investigated the effects of fluorine treatments on the electrical properties and electronic structures of plasma-enhanced atomic layer deposition HfO 2 gate oxides, depending on the treatment process. Pre-and postoxide-deposition fluorine treatments were carried out using CF 4 plasma. Improved dielectric properties were achieved by predeposition treatment, while degradation of electrical properties was observed for postdeposition treatment. Based on the electronic structure analysis using X-ray photoemission spectroscopy and near-edge X-ray absorption fine structures, we found that the enhanced dielectric properties of the pretreated HfO 2 are induced by the defect passivation and conduction-band offset increase.

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Section: Resultssupporting

confidence: 92%

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confidence: 99%

Effects of Fluorine Plasma Treatment on the Electronic Structure of Plasma-Enhanced Atomic Layer Deposition HfO[sub 2]

Maeng

Son

2009

J. Electrochem. Soc.

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“…On the contrary, the F concentrations at the interfaces show a significant increase after the additional annealing process with annealing temperature and time. Si-F bonds are stronger and more difficult to break under stress than Si-H and Si-Cl bonds [21][22][23]; thus, we chose an additional FGA process at 450 °C for 60 min as our optimized annealing condition for fabricating the annealingoptimized p-FinFETs, as shown in Fig. 1a.…”

Section: Resultsmentioning

confidence: 99%

Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization

Zhou

Liu

Yang

et al. 2021

IEEE J. Electron Devices Soc.

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In this paper, we present an experimental study on the impact of post-metallization annealing conditions on the negative-bias temperature instability (NBTI) of Si p-channel fin field-effect transistors (p-FinFETs) with atomic layer deposition tungsten (ALD W) as the gate-filling metal. The effects of annealing conditions on the tensile stress of the W film, impurity element concentration in the gate stack, fresh interface quality, threshold voltage shift (ΔVT), pre-existing traps (ΔNHT), generated traps, and their relative contributions were studied. The time exponents of ΔVT, the impacts of stress bias and temperature on NBTI degradation, and the recovery kinetics of the generated traps were analyzed. For devices with a B2H6-based W-filling metal, a 34% reduction in the fresh interface states, reduced ΔVT, and a 29% improvement in the operation overdrive voltage could be achieved by optimizing the annealing conditions. The NBTI is alleviated mainly because of the reduction in the generated traps, while the energy distribution of ΔNHT is insensitive to the annealing conditions. Furthermore, the relative contribution of the generated bulk insulator traps to the total number of generated traps could be reduced by optimizing the annealing conditions.

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“…Several fluorine passivation technologies have been mentioned to improve device reliabilities, such as tetrafluoromethane ͑CF 4 ͒ plasma treatment, 8 channel fluorine implantation, 9 source/drain region fluorine implantation, 10 and F 2 gas anneal. 11 In this letter, a fluorination process using fluorinated silicate glass ͑FSG͒ passivation layer has been introduced. The electrical characteristics and dielectric reliabilities of n-channel metal-oxide-semiconductor fieldeffect-transistors ͑nMOSFETs͒ with the FSG fluorinated HfO 2 / SiON gate dielectric has been investigated comprehensively.…”

Section: Improved Performance and Reliability For Metal-oxide-semiconmentioning

confidence: 99%

Improved performance and reliability for metal-oxide-semiconductor field-effect-transistor with fluorinated silicate glass passivation layer

Hsieh

Chen

Lou

2010

Applied Physics Letters

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Characterization of fast charge trapping in bias temperature instability in metal-oxide-semiconductor field effect transistor with high dielectric constant Appl. Phys. Lett. 96, 142110 (2010); 10.1063/1.3384999 Enhancement mode GaAs metal-oxide-semiconductor field-effect-transistor integrated with thin AlN surface passivation layer and silicon/phosphorus coimplanted source/drain J.Effective surface passivation methodologies for high performance germanium metal oxide semiconductor field effect transistors Appl. Phys. Lett. 93, 192115 (2008); 10.1063/1.3028025Fabrication of gate stack with high gate work function for implantless enhancement-mode GaAs n -channel metal-oxide-semiconductor field effect transistor applicationsThe superior characteristics of the fluorinated HfO 2 / SiON gate dielectric are investigated comprehensively. Fluorine is incorporated into the gate dielectric through fluorinated silicate glass ͑FSG͒ passivation layer to form fluorinated HfO 2 / SiON dielectric. Fluorine incorporation has been proved to eliminate both bulk and interface trap densities due to Hf-F and Si-F bonds formation, which can strongly reduce trap generation as well as trap-assisted tunneling during subsequently constant voltage stress, and results in improved electrical characteristics and dielectric reliabilities. The results clearly indicate that the fluorinated HfO 2 / SiON gate dielectric using FSG passivation layer becomes a feasible technology for future ultrathin gate dielectric applications.

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Effect of $\hbox{F}_{2}$ Postmetallization Annealing on the Electrical and Reliability Characteristics of HfSiO Gate Dielectric

Cited by 16 publications

References 12 publications

Effects of Fluorine Plasma Treatment on the Electronic Structure of Plasma-Enhanced Atomic Layer Deposition HfO[sub 2]

Effects of Fluorine Plasma Treatment on the Electronic Structure of Plasma-Enhanced Atomic Layer Deposition HfO[sub 2]

Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization

Improved performance and reliability for metal-oxide-semiconductor field-effect-transistor with fluorinated silicate glass passivation layer

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