Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization

Abstract

In this paper, we present an experimental study on the impact of post-metallization annealing conditions on the negative-bias temperature instability (NBTI) of Si p-channel fin field-effect transistors (p-FinFETs) with atomic layer deposition tungsten (ALD W) as the gate-filling metal. The effects of annealing conditions on the tensile stress of the W film, impurity element concentration in the gate stack, fresh interface quality, threshold voltage shift (ΔVT), pre-existing traps (ΔNHT), generated traps, and their relative contributions were studied. The time exponents of ΔVT, the impacts of stress bias and temperature on NBTI degradation, and the recovery kinetics of the generated traps were analyzed. For devices with a B2H6-based W-filling metal, a 34% reduction in the fresh interface states, reduced ΔVT, and a 29% improvement in the operation overdrive voltage could be achieved by optimizing the annealing conditions. The NBTI is alleviated mainly because of the reduction in the generated traps, while the energy distribution of ΔNHT is insensitive to the annealing conditions. Furthermore, the relative contribution of the generated bulk insulator traps to the total number of generated traps could be reduced by optimizing the annealing conditions.

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

“…Other types of III-V nanowires, e.g., InAs and GaSb, were also reported to be integrated for Si-GAAFETs. Among these studies, for example, Z. Zhu et al [336] reported a vertical NW p-MOSFET with the GaSb channel by applying digital etch (DE) schemes. Figure 37a shows the schematic of a single NW-GAA MOSFET.…”

“…However, crystal quality optimization for Si-based III-V materials is still very challenging to achieve good device performance. prior to high-κ deposition [336]. Reproduced from [336], open access by ACS, 2022.…”

“…To achieve a monolithic integration of III-V devices on the Si platform, it is important to develop a heteroepitaxy approach. There are some challenges for high-quality III-V heteroepitaxy on Si such as antiphase boundary (APB) and threading dislocation density (TDD) [329][330][331][332][333][334][335][336][337][338]. Y.…”

“…Even though high-epitaxy-quality III-V materials can be utilized for GAAFET or optoelectronic applications, the vertical geometry can be complicated in terms of device [336]. Reproduced from [336], open access by ACS, 2022.…”

“…Figure 37. (a) Schematic image of a single NW MOSFET with GaSb channel where digital etching was used as the first step of the process; (b) SEM micrograph of a single NW transistor after defining the gate length; (c) transfer characteristics of the NW transistor with two-cycle DE-HCl:IPA 1:10 prior to high-κ deposition[336]. Reproduced from[336], open access by ACS, 2022.…”