Interfacial Layer-Induced Mobility Degradation in High-kTransistors

Abstract

Analysis of electrical and scanning transmission electron microscopy (STEM) and electron energy loss spectra (EELS) data suggests that Hf-based high-k dielectrics deposited on a SiO 2 layer modifies the oxygen content of the latter resulting in reduction of the oxide energy band gap and correspondingly increasing its k value. High-k deposition on thinner SiO 2 films, below 1.1 nm, may lead to the formation of a highly oxygen deficient amorphous interfacial layer adjacent to the Si substrate. This layer was identified as an important factor contributing to mobility degradation in high-k transistors.

The Pulsed Id-Vgmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

“…1). During gate stack fabrication, the interfacial layer can be engineered or it can grow spontaneously [33,78,92,93]. The FTCE can be influenced by these two layers as well as by the amount of hafnium in the high-κ layer.…”

“…In the linear regime, the FTCE can significantly impact mobility [31,63,64,66,79,83,91,92,[96][97][98]. In a conventional DC sweep of the I d -V g measurement, the threshold voltage shifts as the measurement progresses, thereby decreasing the drive current at each bias sweep point resulting in decreased mobility.…”

“…As the interface becomes thinner, the difference between the pulsed and DC mobility for a given gate stack becomes greater. The overall degradation in the pulsed (intrinsic) mobility as the interface layer becomes thinner can be attributed to poorer interfacial layer quality [102] and greater effects of soft optical phonons [64] and crystallinity [21,103].…”

The role of nitrogen-related defects in high-k dielectric oxides: Density-functional studies

“…The low quality of the resulting interfacial SiO x layer negatively impacts transistor characteristics. 17 In order to suppress the suboxide growth, nitrogen-rich ambients are preferable in PDA. 4 In general, nitrogen incorporation into the Hf-based dielectrics was shown to provide several advantages, such as reducing boron penetration from the p-type polysilicon gate electrodes, improving electrical performance, and increasing stability of high-k devices.…”

Impact of High-<I>κ</I> Gate Stacks on Transport and Variability in Nano-CMOS Devices

“…Very little is known about the precise stoichiometry (x value) of the SiO x layer. However, in many gate stacks studied, [53][54][55] an interfacial layer of SiO 2 is intentionally grown in order to control the surface roughness characteristics and to reduce the interface state density and the interaction between electrons and the SO phonons associated with the high-dielectric.…”