Impact of High-<I>κ</I> Gate Stacks on Transport and Variability in Nano-CMOS Devices

Abstract

Scaling of Si MOSFETs beyond the 90 nm technology node requires performance boosters in order to satisfy the International Technology Roadmap for Semiconductors (ITRS) requirements for drive current in high-performance transistors. Amongst the preferred near term solutions are transport enhanced FETs utilising strained Si (SSi) channels. Additionally, high-dielectrics are expected to replace SiO 2 around or after the 45 nm node to reduce the associated gate leakage current problem, facilitating further scaling. However, in spite of significant recent technological achievements, in particular, in reducing charge trapping and crystallization of the dielectric, mobility degradation in the devices with the high-gate stacks caused, in part, by the strong soft optical phonon scattering leaves room for further performance improvement. In this work we study the impact of soft optical phonon scattering on the mobility and device performance for conventional and strained Si n-MOSFETs with high-dielectrics using a self-consistent Poisson Ensemble Monte Carlo device simulator, with effective gate lengths of 67 and 35 nm.

Simulation of statistical variability in nano-CMOS transistors using drift-diffusion, Monte Carlo and non-equilibrium Green’s function techniques

“…8(a) and variability due to work-function variation due to the metal gate granularity illustrated in Fig. 8(b) [28]. In extremely scaled transistors atomic scale interface roughness illustrated in Fig.…”

FOSS as an efficient tool for extraction of MOSFET compact model parameters

“…At the same time they preserve the gate control over the channel conduction. However, due to their polycrystalline morphology the HK dielectrics introduce a dispersion of a the gate leakage to the total MOSFET performance variability [6].…”

Performance Analysis of Nanoscale Double Gate MOSFETs with High-κ Gate Stack

“…Recently, MOSFETs with high-κ gate stack have been presented in literature. Performance of bulk MOSFETs with high-κ gate stack has been studied in [6]. In [5], the device design methodology with DG high-κ gate stack has been reported to give the maximum on-current for a specified offcurrent.…”