Integration issues of high-k gate stack: Process-induced charging

Bersuker, G.; Gutt, J.; Chaudhary, Nirmal; Moumen, N.; Lee, Byoung Hun; Barnett, Joel; Gopalan, Sundararaman; Brown, George; Kim, Y.; Young, C.D.; Peterson, John J.; Li, H.-J.; Zeitzoff, P.; Sim, Gyu-Hyoung; Lysaght, P.; Gardner, Mark; Murto, Robert W.; Huff, Howard R.

doi:10.1109/relphy.2004.1315375

Cited by 10 publications

(5 citation statements)

References 2 publications

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“…To avoid damaging the substrate in the S/D areas, the gate stack dry etch was stopped before the high-k layer is entirely removed. The remaining exposed high-k material was removed to prevent a process-induced charging (PIC) effect on the gate dielectric under the gate [36]. PIC occurs when the subsequent plasma process and ion implantation steps generate negative ions in the exposed high-k material that diffuse easily into the channel dielectric from the S/D areas.…”

Section: Optimization Of Gate Stack Dry Etch and High-k Removal Processmentioning

confidence: 99%

“…The resulting negative charge in the dielectric produces a positive V T shift in the device. It has been proposed that the PIC effect becomes less as high-k gets thinner [36]. It is not clear, though, about the PIC effect, when the high-k dielectric is ultra thin (less than 20Å) that shows negligible charge trapping behavior.…”

Section: Optimization Of Gate Stack Dry Etch and High-k Removal Processmentioning

confidence: 99%

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High Performance Metal Gate CMOSFETs with Aggressively Scaled Hf-Based High-k

Song¹,

Zhang

Bae³

et al. 2006

ECS Trans.

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The optimization of MOSFET performance with Hf-based high-k and TiN metal gate is discussed. MOSFET performance and mobility of metal and poly gate on both high-k and SiO2 are compared. Optimization of the thickness and composition of Hf-silicate is discussed in terms of charge trapping and boron diffusion. The effect of metal gate thickness is also investigated. Appropriate dry and wet etch processes are found to effectively eliminate the metal foot and high-k undercut. Impressive Ion- Ioff characteristics have been achieved by applying an optimized gate-first CMOS flow to the high-k/metal stack. Ion = 1100µA/µm and 540µA/µm was attained for N and PMOSFETs with Vdd = 1.2V and Ioff = 100nA/µm.

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Section: Optimization Of Gate Stack Dry Etch and High-k Removal Processmentioning

confidence: 99%

Section: Optimization Of Gate Stack Dry Etch and High-k Removal Processmentioning

confidence: 99%

High Performance Metal Gate CMOSFETs with Aggressively Scaled Hf-Based High-k

Song¹,

Zhang

Bae³

et al. 2006

ECS Trans.

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“…After gate patterning, the high-layer is removed with a wet etch process leaving minimal damage in the extension region. Then, lightly doped drain and halo dopants are implanted and a thin nitride layer ( 5 nm) is deposited to prevent process induced damage through plasma process or oxygen diffusion [7]. After the thin nitride deposition, 100-nm oxide spacer is formed and the source/drain (S/D) is implanted with As and B and activated using 1000 C, 10-s rapid thermal anneal in N ambient.…”

Section: Methodsmentioning

confidence: 99%

Improved interface quality and charge-trapping characteristics of MOSFETs with high-/spl kappa/ gate dielectric

Park

Rahman

Chang

et al. 2005

IEEE Electron Device Lett.

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The effects of high-pressure annealing on interface properties and charge trapping of nMOSFET with high-dielectric were investigated. Comparing with conventional forming gas (H 2 Ar = 4% 96%) annealed sample, nMOSFET sample annealed in high-pressure (5-20 atm), pure H 2 ambient at 400 C shows 10%-15% improvements in linear drain current ( ) and maximum transconductance ( max ). Interface trap density and charge trapping properties were characterized with charge pumping measurements and "single pulsed" -measurements where reduced interface state density and improved charge trapping characteristics were observed after high pressure annealing. These results indicate that high pressure pure hydrogen annealing can be a crucial process for future high-gate dielectric applications.

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“…Another challenge is removal of the high-k dielectric in the S/D area. The dielectric must be removed thoroughly to prevent any process induced charge effect [12], which causes parameter drift and degrades performance. HfO 2 dielectric is difficult to wet etch with HF chemistry once the HfO 2 is crystallized, but it can be wet etched if it is first subjected to physical bombardment.…”

Section: Fig 2 Schematic Process Flow Of Gate Last (Or Replacement Ga...mentioning

confidence: 99%

Integration Challenges and Opportunities for Nanometer Scale CMOSFET with Metal/High-k Gate Stack

Song¹,

Hussain²,

Barnett³

et al. 2007

ECS Trans.

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As MOSFET scales below 45nm, conventional SiO 2 cannot sustain equivalent oxide thickness (EOT) and leakage current requirements set in the International Technology Roadmap for Semiconductors (ITRS), due to the limitation of physical-thickness scaling, and high tunneling current [1]. Metal gate and high-k dielectric have been extensively studied to overcome the limitation of conventional poly gate and SiO 2 technology. Although recent advancements of the technology enable the metal gate and high-k dielectric to be implemented in actual manufacturing, several issues remain associated with integrating the new materials in CMOS field-effect transistors (FETs). This paper will introduce various integration schemes for fabricating dual metal gate CMOSFET, and review pros and cons of each approach to propose general integration guide for the desired application. Comparison between Gate First and Gate Last IntegrationA metal gate and high-k dielectric can be integrated into the MOSFET process using either a gate-first or gate-last approach. These approaches differ primarily in whether the metal gate is deposited before or after the source/drain (S/D) activation anneal. Fig. 1 Typical process flow for gate first MOSFET flow with TEM cross section of MOSFET and metal/high-k stack

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Integration issues of high-k gate stack: Process-induced charging

Cited by 10 publications

References 2 publications

High Performance Metal Gate CMOSFETs with Aggressively Scaled Hf-Based High-k

High Performance Metal Gate CMOSFETs with Aggressively Scaled Hf-Based High-k

Improved interface quality and charge-trapping characteristics of MOSFETs with high-/spl kappa/ gate dielectric

Integration Challenges and Opportunities for Nanometer Scale CMOSFET with Metal/High-k Gate Stack

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