The equivalent oxide thickness ͑EOT͒ of high-k n-channel metal oxide semiconductor ͑NMOS͒ transistors was scaled using 3 methods, ͑i͒ reduction of the bottom interfacial layer ͑BIL͒ using NH 3 interface engineering, (ii) thickness reduction of the HfO 2 dielectric, and (iii) use of metal gate electrodes to minimize top interfacial growth formation and polysilicon depletion. NMOS transistors fabricated using these methods demonstrate 0.72 nm EOT using the NH 3 BIL with scaled HfO 2 /metal gates and 0.81 nm EOT using the O 3 BIL with scaled HfO 2 /metal gates. Charge pumping, mobility, and device performance results of these high-k NMOS transistors is discussed.
We have demonstrated a uniform, robust interface for high-k deposition with significant improvements in device electrical performance compared to conventional surface preparation techniques. The interface was a thin thermal oxide that was grown and then etched back in a controlled manner to the desired thickness. Utilizing this approach, an equivalent oxide thickness (EOT) as low as 0.87 nm has been demonstrated on high-k gate stacks having improved electrical characteristics as compared to more conventionally prepared starting surfaces.
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