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Analysis of electrical and scanning transmission electron microscopy (STEM) and electron energy loss spectra (EELS) data suggests that Hf-based high-k dielectrics deposited on a SiO 2 layer modifies the oxygen content of the latter resulting in reduction of the oxide energy band gap and correspondingly increasing its k value. High-k deposition on thinner SiO 2 films, below 1.1 nm, may lead to the formation of a highly oxygen deficient amorphous interfacial layer adjacent to the Si substrate. This layer was identified as an important factor contributing to mobility degradation in high-k transistors.

Reduced metal contamination levels become ever more critical as ultralarge scale integrated device feature sizes shrink to 0.25 p.m. Wafers may be contaminated with metals during their manufacture, but metals are more likely to be introduced at the wafer surface during integrated circuit processing. During high-temperature processing steps, the surface contaminants diffuse rapidly into the wafer bulk. Because carrier lifetime and diffusion length are strongly affected by the presence of parts per trillion levels of electrically active metal-related defect centers in the bulk of the wafer, these properties can be used to detect the presence of metal contamination. Unfortunately, these techniques are sometimes misused and misinterpreted. The more common techniques, their benefits, and limitations on their interpretation are discussed. A unified taxonomy to describe carrier lifetime characteristics is also proposed.

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Changes in the composition of atomic layer deposited, uncapped hafnium dioxide films, as a function of anneal temperature, have been evaluated by several advanced analytical techniques including; x-ray reflectivity, high-resolution transmission electron microscopy, and medium energy ion scattering. It is shown that such measurements of the high-k/Si interface layer are inconclusive and may be misinterpreted to suggest the presence of an HfxSi1−xO2 (x∼0.5) transition layer. It is also demonstrated that high-temperature anneal of uncapped films may result in the formation of voids which propagate through the dielectric layer into the silicon substrate. Trends associated with defect generation, interfacial oxide growth, and the low probability of material intermixing during anneal processing are discussed.

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