Gate stack technology for nanoscale devices

Lee, Byoung Hun; Oh, Jungwoo; Tseng, Hsing Huang; Jammy, R.; Huff, Howard R.

doi:10.1016/s1369-7021(06)71541-3

Cited by 175 publications

(88 citation statements)

References 94 publications

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“…In pMOS stack, one of the challenges encountered is the aggressive V fb shift to the negative direction, particularly, the V fb roll-off phenomenon that emerges with scaling of the interlayer SiO 2 (IL SiO 2 ) [30]. As discussed above, the V fb shift is influenced by the interface dipole.…”

Section: Fb Modulation With Al Incorporation In Pmosmentioning

confidence: 99%

Interface dipole engineering in metal gate/high-k stacks

et al. 2012

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Although metal gate/high-k stacks are commonly used in metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the 45 nm technology node and beyond, there are still many challenges to be solved. Among the various technologies to tackle these problems, interface dipole engineering (IDE) is an effective method to improve the performance, particularly, modulating the effective work function (EWF) of metal gates. Because of the different electronegativity of the various atoms in the interfacial layer, a dipole layer with an electric filed can be formed altering the band alignment in the MOS stack. This paper reviews the interface dipole formation induced by different elements, recent progresses in metal gate/high-k MOS stacks with IDE on EWF modulation, and mechanism of IDE. high-k dielectrics, metal gate, interface dipole, MOS stack, effective work function Citation:Huang A P, Zheng X H, Xiao Z S, et al. Interface dipole engineering in metal gate/high-k stacks. Chin Sci Bull, 2012, 57: 28722878, doi: 10.1007/s11434-012-5289-6As poly-Si/SiO 2 is replaced by metal gate/high-k stacks in the 45 nm MOS technological node and beyond, the interface becomes more complicated and there are still many challenges to be solved [1,2], such as the flatband voltage shift (V fb shift) [3]. Hence, the properties of the high-k layer must be reconsidered carefully. It has recently been reported that the interface dipole can induce potential difference across the interface and change the band alignment of the MOS stack, and this phenomenon can be exploited to modulate the V fb shift [4][5][6]. Elemental doping can also improve the performance of the high-k layer. Interface dipole engineering (IDE) by varying the dopants or inserting capping layers has attracted much attention in MOS technology. Not only can this technique control the V fb shift, but also the properties of the high-k dielectrics can be improved [7]. This paper reviews the formation of interface dipole, recent research progresses on IDE and effective work function (EWF) modulation, as well as mechanism of IDE in metal gate/high-k MOS stacks. Interface dipole formation in MOS stackTo control the threshold voltage (V th ), work function of a metal gate should be near the conduction band of Si (~4.3 eV) for nMOS and valence band (~5.2 eV) for pMOS. However, only very few metals can satisfy these requirements and furthermore, when a metal is in contact with the high-k layer, its Fermi-level will tend to be at the neutral level of the high-k layer. This phenomenon is called Fermi-level pinning (FLP) which causes EWF of the nMOS (pMOS) to be much greater (smaller) than the corresponding work function in vacuum [8]. The electron density in the metal gate can also influence the EWF [9]. Stacked metal layers used in the gate structure have been investigated. Misra et al. [10] reported that a metal gate stack using Ru-Ta alloys could yield a work function compatible with nMOS. Lin et al. [11] implanted N into a Mo gate that was

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Section: Fb Modulation With Al Incorporation In Pmosmentioning

confidence: 99%

Interface dipole engineering in metal gate/high-k stacks

et al. 2012

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“…6,17 Concomitantly, it is widely recognized that integration of rare earth-based high-k dielectrics with a high carrier mobility Ge channel can pave the way for realizing sub-22 nm CMOS transistors with increased performance provided that efficient Ge surface passivation is achieved. 18,19 In this context, a comparative study 20 between La 2 O 3 / Ge and La 2 O 3 / Si interfaces addressing IL thickness evolution after postdeposition annealing has revealed that the latter phenomenon is notably smaller for the Ge case than for the Si case, thus, indicating that the former interface might better serve future EOT scalability requirements than the latter one. Along these lines, a detailed investigation is mandatory in order to gain insight as to why low k values ͑k ϳ 14-22͒ compared to the expected value ͑k ϳ 27͒ corresponding to the pure h-La 2 O 3 phase 6,7 have been reported [20][21][22][23] so far for the La 2 O 3 / Ge stacks.…”

Section: Introductionmentioning

confidence: 99%

O 3 -based atomic layer deposition of hexagonal La2O3 films on Si(100) and Ge(100) substrates

Lamagna

Wiemer

Perego

et al. 2010

Journal of Applied Physics

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The hexagonal phase of La2O3 is obtained upon vacuum annealing of hydroxilated La2O3 films grown with atomic layer deposition at 200 °C using La(PirCp)3 and O3. A dielectric constant value of 24±2 and 22±1 is obtained on Si-based and Ge-based metal-oxide-semiconductor capacitors, respectively. However, the relatively good La2O3 dielectric properties are associated with significant interface reactivity on both semiconductor substrates. This leads to the identification of a minimum critical thickness that limits the scaling down of the equivalent oxide thickness of the stack. These findings are explained by the spontaneous formation of lanthanum silicate and germanate species which takes place during the growth and also upon annealing. Although the ultimate film thickness scalability remains an unsolved concern, the use of an O3-based process is demonstrated to be a suitable solution to fabricate La2O3 films that can be successfully converted into the high-k hexagonal phase.

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“…However, in sub-45-nm complementary metal oxide semiconductor (CMOS) technology, the scaling of SiO 2 gate dielectric thickness leads to an unacceptable gate leakage current, which affects the reliability of the device and causes an increase in static power dissipation. Therefore, new kinds of dielectric materials with high permittivity are needed to replace the traditional SiO 2 gate dielectric to obtain a smaller equivalent oxide thickness (EOT) in the CMOS industry [1,2]. Presently, the use of HfO 2 (k~13 to 20) as the gate dielectric in the high-k/metal gate structure has been successfully applied to MOSFET fabrication and is gradually replacing the traditional SiO 2 /poly-Si gate structure [3].…”

Section: Introductionmentioning

confidence: 99%

Silicon diffusion control in atomic-layer-deposited Al2O3/La2O3/Al2O3 gate stacks using an Al2O3 barrier layer

Wang¹,

Liu²,

Fei³

et al. 2016

Nano Online

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In this study, the physical and electrical characteristics of Al 2 O 3 /La 2 O 3 /Al 2 O 3 /Si stack structures affected by the thickness of an Al 2 O 3 barrier layer between Si substrate and La 2 O 3 layer are investigated after a rapid thermal annealing (RTA) treatment. Time of flight secondary ion mass spectrometry (TOF-SIMS) and X-ray photoelectron spectroscopy (XPS) tests indicate that an Al 2 O 3 barrier layer (15 atomic layer deposition (ALD) cycles, approximately 1.5 nm) plays an important role in suppressing the diffusion of silicon atoms from Si substrate into the La 2 O 3 layer during the annealing process. As a result, some properties of La 2 O 3 dielectric degenerated by the diffusion of Si atoms are improved. Electrical measurements (C-V, J-V) show that the thickness of Al 2 O 3 barrier layer can affect the shift of flat band voltage (V FB ) and the magnitude of gate leakage current density.

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Gate stack technology for nanoscale devices

Cited by 175 publications

References 94 publications

Interface dipole engineering in metal gate/high-k stacks

Interface dipole engineering in metal gate/high-k stacks

O 3 -based atomic layer deposition of hexagonal La2O3 films on Si(100) and Ge(100) substrates

Silicon diffusion control in atomic-layer-deposited Al2O3/La2O3/Al2O3 gate stacks using an Al2O3 barrier layer

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