High-k gate stacks for planar, scaled CMOS integrated circuits

Huff, Howard R.; Hou, Tuo‐Hung; Lim, Cheol Hee; Kim, Y.; Barnett, Joel; Bersuker, G.; Brown, George; Young, C.D.; Zeitzoff, P.; Gutt, J.; Lysaght, P.; Gardner, Mark; Murto, Robert W.

doi:10.1016/s0167-9317(03)00292-2

Cited by 58 publications

(23 citation statements)

References 56 publications

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“…However, the integration of high-k dielectrics in Si-based field effect transistors reveals problems such as channel mobility degradation. [5][6] Modified substrates, such as strained Si, SiGe, or Ge layers, [7] promise a partial recovery of channel mobility towards the values obtained for SiO 2 /Si structures. In this work, a MOCVD approach for the deposition of hafnium silicate (Hf x Si y O z ) films for gate dielectric application in MOS capacitors will be presented.…”

Section: Introductionmentioning

confidence: 99%

MOCVD of Hafnium Silicate Films Obtained from a Single‐Source Precusor on Silicon and Germanium for Gate‐Dielectric Applications

Lemberger

Schön

Dirnecker

et al. 2007

Chemical Vapor Deposition

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In this work, hafnium silicate layers on Si and Ge wafers for gate dielectric application in metal-oxide-semiconductor devices are investigated. Films are deposited by metal-organic (MO)CVD using the single-source precursor Hf(acac) 2 (OSi t BuMe 2 ) 2 .This precursor exhibits good properties in terms of hydrolysis stability, volatility, and deposition. However, precursor decomposition is affected by surface conditions. Films deposited on Si wafers reveal high C contamination (up to 20 at %) and low Si content (up to 20 at %). In contrast, for film deposition on Ge wafers, no C contamination can be detected and Si incorporation is delayed until after about 15 nm HfO 2 dielectric growth. Post-deposition rapid thermal annealing in an O 2 atmosphere causes crystallization of deposited films, Si and Ge redistribution in the dielectric, respectively, and interfacial layer growth. However, oxygen annealing was also found to reduce effective oxide thickness (EOT) significantly compared to as-deposited films, which is attributed to crystallization effects. However, scaling of EOT is limited by that interfacial layer growth. Leakage currents are mainly caused by trap-related conduction mechanisms. Energy levels of involved traps decrease with increasing crystallization and/or Hf content, and values of 0.5 eV and 1 eV related to Hf and Si bonds, respectively, are obtained.

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Section: Introductionmentioning

confidence: 99%

MOCVD of Hafnium Silicate Films Obtained from a Single‐Source Precusor on Silicon and Germanium for Gate‐Dielectric Applications

Lemberger

Schön

Dirnecker

et al. 2007

Chemical Vapor Deposition

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“…The study of high-k dielectrics as a replacement for SiO 2 in complementary metal-oxide-semiconductor devices has become a field of enormous interest. [1][2][3] In this letter, we investigate the band-offset characteristics of high-k dielectrics on silicon. We utilize internal photoemission spectroscopy, a simple optical method developed in the 1960s, 4,5 which has seen recent renewed interest in order to gain information about barrier heights, trap states and interface dipoles in high-k dielectrics.…”

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confidence: 99%

Determination of energy barrier profiles for high-k dielectric materials utilizing bias-dependent internal photoemission

Brewer

Walters

Bell

et al. 2004

Applied Physics Letters

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We utilize bias-dependent internal photoemission spectroscopy to determine the metal/dielectric/ silicon energy barrier profiles for Au/ HfO 2 / Si and Au/ Al 2 O 3 / Si structures. The results indicate that the applied voltage plays a large role in determining the effective barrier height and we attribute much of the variation in this case to image potential barrier lowering in measurements of single layers. By measuring current at both positive and negative voltages, we are able to measure the band offsets from Si and also to determine the flatband voltage and the barrier asymmetry at 0 V. Our SiO 2 calibration sample yielded a conduction band offset value of 3.03± 0.1 eV. Measurements on HfO 2 give a conduction band offset value of 2.7± 0.2 eV (at 1.0 V) and Al 2 O 3 gives an offset of 3.3± 0.1 (at 1.0 V). We believe that interfacial SiO 2 layers may dominate the electron transport from silicon for these films. The Au/ HfO 2 barrier height was found to be 3. The study of high-k dielectrics as a replacement for SiO 2 in complementary metal-oxide-semiconductor devices has become a field of enormous interest. [1][2][3] In this letter, we investigate the band-offset characteristics of high-k dielectrics on silicon. We utilize internal photoemission spectroscopy, a simple optical method developed in the 1960s, 4,5 which has seen recent renewed interest in order to gain information about barrier heights, trap states and interface dipoles in high-k dielectrics. 6 In this technique, a bias is applied across a dielectric structure, while tunable monochromatic light shines on the sample. At a threshold photon energy, electrons from the substrate (or metal gate) are excited by internal photoemission over the dielectric barrier. 7 This threshold energy corresponds to the barrier height of the dielectric. Using bias-dependent internal photoemission spectroscopy, we have determined a barrier height profile as a function of voltage. By measuring the barrier height at both positive and negative voltages, band offsets with respect to silicon (and also the metal gate) can be determined in addition to the flatband voltage and barrier asymmetry at 0 V.In our experimental system, we utilize a 1000 W Hg-Xe lamp with a monochromator as our light source. We use a voltage source/femtoammeter to apply the bias across the sample and to measure the current at each bias. The system is computer controlled by LabView so that the light can be scanned between 1 and 6 eV at any bias and photon energy step size. A multifunction optical meter is used to determine the lamp output spectrum to normalize the photoemission yield. Fused silica lenses are used to focus the light onto the top gold contact of the sample, which is held vertically.The dielectric samples are grown on degenerately phosphorous doped n-type silicon to minimize the voltage drop across the depletion region in the silicon, and enhance the accuracy of our measurement. The dielectrics presented in this letter are HfO 2 and Al 2 O 3 grown by atomic layer deposition. 8,9 Before depo...

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“…A high-k oxide would provide a higher effective capacitance to a comparable SiO 2 layer, hence allowing thicker layers to be used to reduce losses due to tunneling. The specific choice of oxide is determined by a set of requirements 46 based on both the intrinsic properties of the grown oxide and its integration into the fabrication process, and at present hafnium oxide ͑HfO 2 ͒ remains a leading candidate.…”

Section: B Thin Insulating Layermentioning

confidence: 99%

Finite-element implementation for electron transport in nanostructures

Havu¹,

Havu²,

Puska³

et al. 2006

The Journal of Chemical Physics

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Articles you may be interested inDeriving k·p parameters from full-Brillouin-zone descriptions: A finite-element envelope function model for quantum-confined wurtzite nanostructures J. Appl. Phys. 116, 033709 (2014) We have modeled transport properties of nanostructures using Green's-function method within the framework of the density-functional theory. The scheme is computationally demanding, so numerical methods have to be chosen carefully. A typical solution to the numerical burden is to use a special basis-function set, which is tailored to the problem in question, for example, the atomic-orbital basis. In this paper we present our solution to the problem. We have used the finite-element method with a hierarchical high-order polynomial basis, the so-called p elements. This method allows the discretation error to be controlled in a systematic way. The p elements work so efficiently that they can be used to solve interesting nanosystems described by nonlocal pseudopotentials. We demonstrate the potential of the implementation with two different systems. As a test system a simple Na-atom chain between two leads is modeled and the results are compared with several previous calculations. Secondly, we consider a thin hafnium dioxide ͑HfO 2 ͒ layer on a silicon surface as a model for a gate structure of the next generation of microelectronics.

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High-k gate stacks for planar, scaled CMOS integrated circuits

Cited by 58 publications

References 56 publications

MOCVD of Hafnium Silicate Films Obtained from a Single‐Source Precusor on Silicon and Germanium for Gate‐Dielectric Applications

MOCVD of Hafnium Silicate Films Obtained from a Single‐Source Precusor on Silicon and Germanium for Gate‐Dielectric Applications

Determination of energy barrier profiles for high-k dielectric materials utilizing bias-dependent internal photoemission

Finite-element implementation for electron transport in nanostructures

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