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The magnitude of the V T instability in conventional MOSFETs and MOS capacitors with SiO 2 /HfO 2 dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO 2 /HfO 2 interface and in the bulk of the HfO 2 layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V T instability in terms of structural defects as follows. 1) A defect band in the HfO 2 layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO 2 /HfO 2 interface by tunneling.

A robust valley polarization is a key prerequisite for exploiting valley pseudospin to carry information in next-generation electronics and optoelectronics. Although monolayer transition metal dichalcogenides with inherent spin–valley coupling offer a unique platform to develop such valleytronic devices, the anticipated long-lived valley pseudospin has not been observed yet. Here we demonstrate that robust valley-polarized holes in monolayer WSe2 can be initialized by optical pumping. Using time-resolved Kerr rotation spectroscopy, we observe a long-lived valley polarization for positive trion with a lifetime approaching 1 ns at low temperatures, which is much longer than the trion recombination lifetime (∼10–20 ps). The long-lived valley polarization arises from the transfer of valley pseudospin from photocarriers to resident holes in a specific valley. The optically initialized valley pseudospin of holes remains robust even at room temperature, which opens up the possibility to realize room-temperature valleytronics based on transition metal dichalcogenides.

We have fabricated a Ti/ TiO 2 / Pt oxide diode with excellent rectifying characteristics by the asymmetric Schottky barriers at the Ti/ TiO 2 ͑0.13 eV͒ and the TiO 2 / Pt ͑0.73 eV͒ interfaces. Instead of homogeneous conduction, the current transport is governed by the localized oxygen-deficient TiO 2 filaments. In addition, the reproducible resistive-switching exists in the same structure, triggered by the forming process. The transition between two modes is ascribed to the destruction of the interface barriers at forming. The rectification stable up to 125°C and 10 3 cycles under Ϯ3 V sweep without interference with resistive-switching shows satisfactory reliability of TiO 2 diodes for one diode-one resistor memory devices.

A bipolar nonlinear selector to suppress the sneak current in the crossbar array has been fabricated using a simple Ni/TiO 2 /Ni metal-insulator-metal structure. The highly nonlinear current-voltage characteristics are realized by the Schottky emission over the Ni/TiO 2 barriers. The series connection with an HfO 2 -resistive memory device shows reproducible bipolar resistive switching. The maximum array size with at least 10% read margin is projected to exceed megabits. This letter demonstrates the promise of the compact one selector-one resistor (1S1R) cell structure for high-density crossbar array applications.

A two-terminal analog synaptic device that precisely emulates biological synaptic features is expected to be a critical component for future hardware-based neuromorphic computing. Typical synaptic devices based on filamentary resistive switching face severe limitations on the implementation of concurrent inhibitory and excitatory synapses with low conductance and state fluctuation. For overcoming these limitations, we propose a Ta/TaOx/TiO2/Ti device with superior analog synaptic features. A physical simulation based on the homogeneous (nonfilamentary) barrier modulation induced by oxygen ion migration accurately reproduces various DC and AC evolutions of synaptic states, including the spike-timing-dependent plasticity and paired-pulse facilitation. Furthermore, a physics-based compact model for facilitating circuit-level design is proposed on the basis of the general definition of memristor devices. This comprehensive experimental and theoretical study of the promising electronic synapse can facilitate realizing large-scale neuromorphic systems.

Precise electrical manipulation of nanoscale defects such as vacancy nano-filaments is highly desired for the multi-level control of ReRAM. In this paper we present a systematic investigation on the pulse-train operation scheme for reliable multi-level control of conductive filament evolution. By applying the pulse-train scheme to a 3 bit per cell HfO2 ReRAM, the relative standard deviations of resistance levels are improved up to 80% compared to the single-pulse scheme. The observed exponential relationship between the saturated resistance and the pulse amplitude provides evidence for the gap-formation model of the filament-rupture process.

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