2018
DOI: 10.1109/jetcas.2017.2771529
|View full text |Cite
|
Sign up to set email alerts
|

Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse

Help me understand this report
View preprint versions

Search citation statements

Order By: Relevance

Paper Sections

Select...
4
1

Citation Types

3
62
0

Year Published

2018
2018
2023
2023

Publication Types

Select...
7
1

Relationship

0
8

Authors

Journals

citations
Cited by 92 publications
(65 citation statements)
references
References 24 publications
3
62
0
Order By: Relevance
“…However, due to device variations, it is usually not straightforward to consider deterministically separated conductance levels and the multi-level capability should be considered in a probabilistic fashion 19 , 32 . Moreover, for specific synaptic applications, some functional non-idealities exist in physical devices that could affect the network performance, such as non linear weight update and asymmetric behaviour between the processes of conductance increase (potentiation) and decrease (depression) 33 , 34 . Several works concentrate on optimizing the material stack to improve the linearity of the conductance change 35 , 36 .…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…However, due to device variations, it is usually not straightforward to consider deterministically separated conductance levels and the multi-level capability should be considered in a probabilistic fashion 19 , 32 . Moreover, for specific synaptic applications, some functional non-idealities exist in physical devices that could affect the network performance, such as non linear weight update and asymmetric behaviour between the processes of conductance increase (potentiation) and decrease (depression) 33 , 34 . Several works concentrate on optimizing the material stack to improve the linearity of the conductance change 35 , 36 .…”
Section: Introductionmentioning
confidence: 99%
“…However, the linear behaviour is usually displayed only up to a certain number of pulses and in a restricted memory window. Another class of researches analyzes the impact of device dynamics and number of conductance levels on the performance of simulated neuromorphic networks 34 , 37 , 38 . Network simulations give some useful hints on how the details of synaptic plasticity influence the learning process 39 , though only theoretical conductance changes or representative device results are routinely considered.…”
Section: Introductionmentioning
confidence: 99%
“…RRAM can be categorized into either filamentary or nonfilamentary, for the RS caused by the restore/rupture of a conductive filament (CF) or the areal modulation of defect distribution inside the oxide, respectively. Both types have been intensively studied for novel synaptic applications [2][3][4][5][6], but there is a lack of comparative analysis between them.…”
Section: Introductionmentioning
confidence: 99%
“…On the other hand, RTN provides useful information on the responsible defect [9,10]. The impact of RTN has been analyzed for CF RRAM [11], but there is a lack of comparative studies on the non-CF (NCF) RRAM whose synaptic application has also drawn extensive interests [4,12].…”
Section: Introductionmentioning
confidence: 99%
“…In order to create negative weights, two weight realization techniques have been introduced: (i) using two RRAM cells per weight [32] as shown in Fig. 4, which is referred to as balanced realization, and (ii) using one RRAM as weight, in addition to one shared reference RRAM with the conductance of G r = (G max + G min )/2 ≈ G max /2, which is referred to as unbalanced realization [26], [33] where G max and G min are the minimum and maximum achievable conductances, respectively. In this work, we consider the first realization, which has double the dynamic range (conductance range ≈ (−G max , G max )), making it less susceptible to noise and variability at the expense of doubling the area and power.…”
Section: B Mvm Using Rcasmentioning
confidence: 99%