IR-QNN Framework: An IR Drop-Aware Offline Training of Quantized Crossbar Arrays

Fouda, Mohammed E.; Lee, Sugil; Lee, Jong-Eun; Kim, Gon−Ho; Kurdahi, Fadi; Eltawi, Ahmed M.

doi:10.1109/access.2020.3044652

Cited by 23 publications

(11 citation statements)

References 46 publications

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“…Second, adapted network training strategies, including Crossbar IR drop phenomenon, allow preventing network accuracy degradation during inference. [27][28][29] Third, including the IR voltage drop constraint when designing the circuit architecture, enhances its robustness to the phenomenon. [29][30][31] In this context, Figure 9A quantifies the trade-off between crossbar area and system accuracy.…”

Section: Binarized Spiking Neural Network Figures Of Meritmentioning

confidence: 99%

1S1R Optimization for High‐Frequency Inference on Binarized Spiking Neural Networks

Lopez

Rafhay

Dampfhoffer

et al. 2022

Adv Elect Materials

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in graphics processing units (GPUs) or central processing units (CPU) remains extremely challenging. On the contrary, the brain promises very high cognitive capacity while preserving exceptional energy efficiency. One of the main differences between GPUs or CPUs and the brain is memory management. On the one hand, a physical separation exists in GPUs and CPUs between arithmetic and storage units, which is at the origin of enormous energy consumption associated with data transfer between both units. [1] This trend is particularly exacerbated for Artificial Neural Networks (ANNs), which require a very large amount of memory access. On the other hand, the biological neurons and synapses are close to each other in the brain. Accordingly, developing non-von-Neumann architectures to perform in or near-memory computing with non-volatile memory (NVM) technologies is one of the most promising strategies to improve the energetic efficiency of artificial intelligence. [2] Another relevant difference between artificial processors and the brain is the way information is coded. On the one hand, GPUs and CPUs rely on high-precision floating-point outputs. On the other hand, binarized sparse and asynchronous spikes are used to communicate in the brain. In particular, a neuron receives through Single memristor crossbar arrays are a very promising approach to reduce the power consumption of deep learning accelerators. In parallel, the emerging bio-inspired spiking neural networks (SNNs) offer very low power consumption with satisfactory performance on complex artificial intelligence tasks. In such neural networks, synaptic weights can be stored in nonvolatile memories. The latter are massively read during inference, which can lead to device failure. In this context, a 1S1R ( 1Selector 1 Resistor) device composed of a HfO 2 -based OxRAM memory stacked on a Ge-Se-Sb-N-based ovonic threshold switch (OTS) back-end selector is proposed for high-density binarized SNNs (BSNNs) synaptic weight hardware implementation. An extensive experimental statistical study combined with a novel Monte Carlo model allows to deeply analyze the OTS switching dynamics based on field-driven stochastic nucleation of conductive dots in the layer. This allows quantifying the occurrence frequency of OTS erratic switching as a function of the applied voltages and 1S1R reading frequency. The associated 1S1R reading error rate is calculated. Focusing on the standard machine learning MNIST image recognition task, BSNN figures of merit (footprint, electrical consumption during inference, frequency of inference, accuracy, and tolerance to errors) are optimized by engineering the network topology, training procedure, and activations sparsity.

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Section: Binarized Spiking Neural Network Figures Of Meritmentioning

confidence: 99%

1S1R Optimization for High‐Frequency Inference on Binarized Spiking Neural Networks

Lopez

Rafhay

Dampfhoffer

et al. 2022

Adv Elect Materials

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“…The unit wordline (bitline) parasitic resistance ranges from approximately 2.5Ω (1Ω) at 45nm node to 10Ω (3.8Ω) at 16nm node. The value of these unit parasitic resistances is expected to scale further reaching ≈ 25Ω at 5nm node [33,35,36,73,92]. The unit wordline and bitline capacitance values also scale proportionately with technology.…”

Section: Latency Variation In a Neuromorphic Pementioning

confidence: 99%

Design-Technology Co-Optimization for NVM-based Neuromorphic Processing Elements

Song¹,

Balaji²,

Das³

et al. 2022

Preprint

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An emerging use-case of machine learning (ML) is to train a model on a high-performance system and deploy the trained model on energy-constrained embedded systems. Neuromorphic hardware platforms, which operate on principles of the biological brain, can significantly lower the energy overhead of a machine learning inference task, making these platforms an attractive solution for embedded ML systems. We present a designtechnology tradeoff analysis to implement such inference tasks on the processing elements (PEs) of a Non-Volatile Memory (NVM)-based neuromorphic hardware. Through detailed circuit-level simulations at scaled process technology nodes, we show the negative impact of technology scaling on the information-processing latency, which impacts the quality-of-service (QoS) of an embedded ML system. At a finer granularity, the latency inside a PE depends on 1) the delay introduced by parasitic components on its current paths, and 2) the varying delay to sense different resistance states of its NVM cells. Based on these two observations, we make the following three contributions. First, on the technology front, we propose an optimization scheme where the NVM resistance state that takes the longest time to sense is set on current paths having the least delay, and vice versa, reducing the average PE latency, which improves the QoS. Second, on the architecture front, we introduce isolation transistors within each PE to partition it into regions that can be individually power-gated, reducing both latency and energy. Finally, on the system-software front, we propose a mechanism to leverage the proposed technological and architectural enhancements when implementing a machine-learning inference task on neuromorphic PEs of the hardware. Evaluations with a recent neuromorphic hardware architecture show that our proposed design-technology co-optimization approach improves both performance and energy efficiency of machine-learning inference tasks without incurring high cost-per-bit. CCS Concepts: • Hardware → Neural systems; Emerging languages and compilers; Emerging tools and methodologies; • Computer systems organization → Data flow architectures; Neural networks.

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“…Despite its promising effectiveness, RCAs come with some challenges such as high peripheral circuit overhead (e.g., analog-to-digital converters [6]) and functional inaccuracy due to device and circuit nonidealities. In particular, nonidealities in RCAs such as stuck-at fault (SAF) [7], [8], IR drop [9]- [12], and device variabilities [13], [14], have been shown to degrade the quality of application results severely. In this paper we focus on SAF, which is a very common problem where a memristor is permanently set to either high-resistance state (HRS) or a low-resistance state (LRS).…”

Section: Introductionmentioning

confidence: 99%

Training-Free Stuck-At Fault Mitigation for ReRAM-Based Deep Learning Accelerators

Quan

Fouda

Lee

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Although Resistive RAMs can support highly efficient matrix-vector multiplication, which is very useful for machine learning and other applications, the non-ideal behavior of hardware such as stuck-at fault and IR drop is an important concern in making ReRAM crossbar array-based deep learning accelerators. Previous work has addressed the nonideality problem through either redundancy in hardware, which requires a permanent increase of hardware cost, or software retraining, which may be even more costly or unacceptable due to its need for a training dataset as well as high computation overhead. In this paper we propose a very light-weight method that can be applied on top of existing hardware or software solutions. Our method, called FPT (Forward-Parameter Tuning), takes advantage of a certain statistical property existing in the activation data of neural network layers, and can mitigate the impact of mild nonidealities in ReRAM crossbar arrays for deep learning applications without using any hardware, a dataset, or gradientbased training. Our experimental results using MNIST, CIFAR-10, CIFAR-100, and ImageNet datasets in binary and multibit networks demonstrate that our technique is very effective, both alone and together with previous methods, up to 20% fault rate, which is higher than even some of the previous remapping methods. We also evaluate our method in the presence of other nonidealities such as variability and IR drop. Further, we provide an analysis based on the concept of effective fault rate, which not only demonstrates that effective fault rate can be a useful tool to predict the accuracy of faulty RCA-based neural networks, but also explains why mitigating the SAF problem is more difficult with multi-bit neural networks.

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IR-QNN Framework: An IR Drop-Aware Offline Training of Quantized Crossbar Arrays

Cited by 23 publications

References 46 publications

1S1R Optimization for High‐Frequency Inference on Binarized Spiking Neural Networks

1S1R Optimization for High‐Frequency Inference on Binarized Spiking Neural Networks

Design-Technology Co-Optimization for NVM-based Neuromorphic Processing Elements

Training-Free Stuck-At Fault Mitigation for ReRAM-Based Deep Learning Accelerators

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