Artificial neural networks are notoriously power- and time-consuming when implemented on conventional von Neumann computing systems. Consequently, recent years have seen an emergence of research in machine learning hardware that strives to bring memory and computing closer together. A popular approach is to realise artificial neural networks in hardware by implementing their synaptic weights using memristive devices. However, various device- and system-level non-idealities usually prevent these physical implementations from achieving high inference accuracy. We suggest applying a well-known concept in computer science—committee machines—in the context of memristor-based neural networks. Using simulations and experimental data from three different types of memristive devices, we show that committee machines employing ensemble averaging can successfully increase inference accuracy in physically implemented neural networks that suffer from faulty devices, device-to-device variability, random telegraph noise and line resistance. Importantly, we demonstrate that the accuracy can be improved even without increasing the total number of memristors.

Selector device is critical in high-density cross-point resistive switching memory arrays for suppressing the sneak leakage current path. GexSe1-x based ovonic threshold switch (OTS) selectors have recently demonstrated strong performance with high on-state current, nonlinearity and endurance. Detailed study of its reliability is still lacking and the understanding on the responsible mechanisms is limited. In this work, for the first time, the endurance degradation mechanism of Ge-rich GexSe1-x OTS is identified. Accumulation of slow defects that remain delocalized at off-state and GeSe segregation/crystallization during cycling lead to the recoverable and non-recoverable leakage current, respectively. Most importantly, a refreshing program scheme is developed to recover and prevent the OTS degradation and the endurance can be therefore improved by more than five orders without adding additional material elements or process steps.

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Neuromorphic computation based on resistive switching devices represents a relevant hardware alternative for artificial deep neural networks. For the highest accuracies on pattern recognition tasks, an analog, linear, and symmetric synaptic weight is essential. Moreover, the resistive switching devices should be integrated with the supporting electronics, such as thin-film transistors (TFTs), to solve crosstalk issues on the crossbar arrays. Here, an a-Indium-gallium-zinc-oxide (IGZO) memristor is proposed, with Mo and Ti/Mo as bottom and top contacts, with forming-free analog switching ability for an upcoming integration on crossbar arrays with a-IGZO TFTs for neuromorphic hardware systems. The development of a TFT compatible fabrication process is accomplished, which results in an a-IGZO memristor with a high stability and low cycle-to-cycle variability. The synaptic behavior through potentiation and depression tests using an identical spiking scheme is presented, and the modulation of the plasticity characteristics by applying non-identical spiking schemes is also demonstrated. The pattern recognition accuracy, using MNIST handwritten digits dataset, reveals a maximum of 91.82% accuracy, which is a promising result for crossbar implementation. The results displayed here reveal the potential of Mo/a-IGZO/Ti/Mo memristors for neuromorphic hardware.

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The future security of Internet of Things is a key concern in the cyber-security field. One of the key issues is the ability to generate random numbers with strict power and area constrains. “True Random Number Generators” have been presented as a potential solution to this problem but improvements in output bit rate, power consumption, and design complexity must be made. In this work we present a novel and experimentally verified “True Random Number Generator” that uses exclusively conventional CMOS technology as well as offering key improvements over previous designs in complexity, output bitrate, and power consumption. It uses the inherent randomness of telegraph noise in the channel current of a single CMOS transistor as an entropy source. For the first time multi-level and abnormal telegraph noise can be utilised, which greatly reduces device selectivity and offers much greater bitrates. The design is verified using a breadboard and FPGA proof of concept circuit and passes all 15 of the NIST randomness tests without any need for post-processing of the generated bitstream. The design also shows resilience against machine learning attacks performed by the LSTM neural network.