In this paper we propose and evaluate the performance of a 3D-embedded neuromorphic computation block based on indium gallium zinc oxide ( -IGZO) based nanosheet transistor and bi-layer resistive memory devices. We have fabricated bi-layer resistive random-access memory (RRAM) devices with Ta2O5 and Al2O3 layers. The device has been characterized and modeled. The compact models of RRAM and -IGZO based embedded nanosheet structures have been used to evaluate the system level performance of 8 vertically stacked -IGZO based nanosheet layers with RRAM for neuromorphic applications. The model considers the design space with uniform bit line (BL), select line (SL) and word line (WL) resistance. Finally, we have simulated the weighted sum operation with our proposed 8-layer stacked nanosheet based embedded memory and evaluated the performance for VGG-16 convolutional neural network (CNN) for Fashion-MNIST and CIFAR-10 data recognition, which yielded 92% and 75% accuracy respectively with drop out layers amid device variation.

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Recent Trends and Prospectshis tutorial introduces the basics of emerging nonvolatile memory (NVM) technologies including spin-transfer-torque magnetic random access memory (STT-MRAM), phase-change random access memory (PCRAM), and resistive random access memory (RRAM). Emerging NVM cell characteristics are summarized, and device-level engineering trends are discussed. Emerging NVM array architectures are introduced, including the onetransistor-one-resistor (1T1R) array and the cross-point array with selectors. Design challenges such as scaling the write current and minimizing the sneak path current in cross-point array are analyzed. Recent progress on megabit-to gigabit-level prototype chip demonstrations is summarized. Finally, the prospective applications of emerging NVM are discussed, ranging from the last-level cache to the storage-class memory in the memory hierarchy. Topics of three-dimensional (3D) integration and radiation-hard NVM are discussed. Novel applications beyond the conventional memory applications are also surveyed, including physical unclonable function for hardware security, reconfigurable routing switch for field-programmable gate array (FPGA), logic-in-memory and nonvolatile cache/register/flip-flop

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The crossbar array architecture with resistive synaptic devices is attractive for on-chip implementation of weighted sum and weight update in the neuro-inspired learning algorithms. This paper discusses the design challenges on scaling up the array size due to non-ideal device properties and array parasitics. Circuit-level mitigation strategies have been proposed to minimize the learning accuracy loss in a large array. This paper also discusses the peripheral circuits design considerations for the neuro-inspired architecture. Finally, a circuit-level macro simulator is developed to explore the design trade-offs and evaluate the overhead of the proposed mitigation strategies as well as project the scaling trend of the neuroinspired architecture.

Energy efficient hardware implementation of artificial neural network is challenging due the 'memory-wall' bottleneck. Neuromorphic computing promises to address this challenge by eliminating data movement to and from off-chip memory devices. Emerging non-volatile memory (NVM) devices that exhibit gradual changes in resistivity are a key enabler of in-memory computing-a type of neuromorphic computing. In this paper, we present a review of some of the NVM devices (RRAM, CBRAM, PCM) commonly used in neuromorphic application. The review focuses on the trade-off between device parameters such as retention, endurance, device-to-device variation, speed and resistance levels, and the interplay with target applications. This work aims at providing guidance for finding the optimized resistive memory devices material stack suitable for neuromorphic application.