NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning

Chen, Pai-Yu; Peng, Xiaochen; Yu, Shimeng

doi:10.1109/tcad.2018.2789723

Cited by 392 publications

(319 citation statements)

References 37 publications

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“…The framework outputs include the hardware-constrained training or inference accuracy (from python wrapper), and hardware metrics such as chip area, latency, dynamic energy, leakage power, as well as energy efficiency and throughput (from NeuroSim core) for training or inference. The modular circuit component estimation are all calibrated by SPICE simulations across technology nodes from 130nm down to 7nm with PTM models [12], as shown in our prior work [13].…”

Section: Figurementioning

confidence: 99%

DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies

Peng

Huang

Luo

et al. 2019

2019 IEEE International Electron Devices Meeting (IEDM)

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203

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DNN+NeuroSim is an integrated framework to benchmark compute-in-memory (CIM) accelerators for deep neural networks, with hierarchical design options from devicelevel, to circuit-level and up to algorithm-level. A python wrapper is developed to interface NeuroSim with a popular machine learning platform: Pytorch, to support flexible network structures. The framework provides automatic algorithm-to-hardware mapping, and evaluates chip-level area, energy efficiency and throughput for training or inference, as well as training/inference accuracy with hardware constraints. Our prior work (open-source framework DNN+NeuroSim V1.1: https://github.com/neurosim/DNN_NeuroSim_V1.1) was developed to estimate the impact of reliability in synaptic devices, and analog-to-digital converter (ADC) quantization loss on the accuracy and hardware performance of inference engines. In this work, we further investigated the impact of the "analog" emerging non-volatile memory (eNVM)'s non-ideal device properties for on-chip training. By introducing the nonlinearity, asymmetry, device-to-device and cycle-to-cycle variation of weight update into the python wrapper, and peripheral circuits for error/weight gradient computation in NeuroSim core, we benchmarked CIM accelerators based on state-of-the-art SRAM and eNVM devices for VGG-8 on CIFAR-10 dataset, revealing the crucial specs of synaptic devices for on-chip training. The proposed DNN+NeuroSim V2.0 framework is available on GitHub at https://github.com/neurosim/DNN_NeuroSim_V2.0.

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Section: Figurementioning

confidence: 99%

DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies

Peng

Huang

Luo

et al. 2019

2019 IEEE International Electron Devices Meeting (IEDM)

Self Cite

203

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“…The LTP and LTD behavior was studied by applying identical 50 B) The HRS step in G-LIST device is stable due to the graphene barrier that avoids the self-diffusion of Li + ion. The LTP and LTD behavior was studied by applying identical 50 B) The HRS step in G-LIST device is stable due to the graphene barrier that avoids the self-diffusion of Li + ion.…”

Section: Resultsmentioning

confidence: 99%

“…Electron. [50,51] Here, nonlinearity analysis is performed using the previously reported weight update formula: [52] 2020, 6, 1901100 Table 1.…”

Section: Wwwadvelectronicmatdementioning

confidence: 99%

Controlled Ionic Tunneling in Lithium Nanoionic Synaptic Transistor through Atomically Thin Graphene Layer for Neuromorphic Computing

Nikam

Kwak

Lee

et al. 2019

Adv Elect Materials

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computers due to the dense neural network of synapses. [3,4] Developing a highspeed and a low-cost artificial synapse device to build an artificial neural network to simulate the human brain like functionalities is the dominant scientific goal of the twenty-first century. Colossal exertion has been committed to developing a synapse device that can trigger the synaptic plasticity and nonvolatility. The conventional neural prototype chip was fabricated based on traditional complementary metal-oxide-semiconductor (CMOS) circuits. [5] However, consumption of high power due to a large number of transistors in COMS circuit limits its further development. [6,7] Besides, a different type of two-terminal memristor such as oxidebased resistive random-access memory (RRAM), [8] ferroelectric memory, [9][10][11][12] and phase-change memory (PCM) [13][14][15] has been employed to mimic the synaptic activity due to reversible analog switching. However, reduced control over conductance change and asynchronous read/write operation limit the application of twoterminal devices as a synaptic element. [16] More recently, a nanoionics synaptic transistor (IST) has been extensively studied and proposed as a suitable candidate for artificial synapses. [17][18][19][20] An IST consists of ionically conducting gate electrolyte and insulating or semiconducting channel. An IST relies on field-driven ion migration from an electrolyte to channel, thereby changing its doping state and hence its conductivity. This device shows reversibility near analog switching, nonvolatility, and low switching energy because of a filamentforming free switching. Additionally, these devices give a high level of accuracy to emulate the synaptic functionalities because synaptic weight update modulated by the gate terminal while the read operation performed on a channel.Recently, several reports show the synaptic behavior by adding and extracting the oxygen (O 2− ) or proton (H + ) in a channel from the electrolyte layer. [17,19,21,22] Both oxygen and proton-based synaptic transistors show unstable behavior and non-linearity due to the structural deformation of a channel as well as the electrolyte layer by mobile H + and O 2− ion. The advantage of using Li + ion in IST is due to more excellent Lithium nanoionic transistors have recently emerged as promising artificial synaptic devices for neuromorphic hardware systems. However, mimicking the essential synaptic functionalities including nonvolatile conductance modulation with a near-linear analog weight update has been a crucial milestone in those synaptic devices and has a direct impact on pattern recognition accuracy. The volatile channel conductance change due to the instability of the solid electrolyte interface and lithium-ion nucleation at electrolyte-channel interface are two key phenomena responsible for the nonlinear switching in lithium nanoionics transistor. Graphene is proposed as an atomically thin ionic tunneling layer to establish nonvolatile analog multilevel conduction in lithium nanoionic transisto...

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“…Realistic cases in which device characteristics affect accuracy are considered e.g. in [29]. 8 The first kind of digital NN is based on SRAM synapses that only provide a weight, while the multiplication and summation (MAC) operations are performed consecutively in the neuron [29].…”

Section: Types Of Neuromorphic Devicesmentioning

confidence: 99%

“…in [29]. 8 The first kind of digital NN is based on SRAM synapses that only provide a weight, while the multiplication and summation (MAC) operations are performed consecutively in the neuron [29]. The circuit considered here follows that in [22]: a synapse consists of n-bits of a SRAM register and state element; a neuron consists of two n-bit registers, an n-bit adder, n NAND gates, n inverters, and three n-state elements.…”

Section: Types Of Neuromorphic Devicesmentioning

confidence: 99%

Benchmarking Delay and Energy of Neural Inference Circuits

Nikonov

Young

2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Numerous neural network circuits and architectures are presently under active research for application to artificial intelligence and machine learning. Their physical performance metrics (area, time, energy) are estimated. Various types of neural networks (artificial, cellular, spiking, and oscillator) are implemented with multiple CMOS and beyond-CMOS (spintronic, ferroelectric, resistive memory) devices. A consistent and transparent methodology is proposed and used to benchmark this comprehensive set of options across several application cases. Promising architecture/device combinations are identified.In the last few years, AI/ML achieved prominent successes, especially related to deep neural networks (DNN) [7] and convolutional neural networks (CoNN). ML has enabled a revolutionary improvement in the accuracy of image, pattern, and facial recognition, including 2 the treatment of 'big data' online. More demand for neural computing is emerging in robotic control, autonomous vehicles, drones, etc.One of the main concerns on the minds of developers of AI computing systems is the same as for traditional computing: the power consumption in the chips. The history of traditional computing shows that the commercial success of computing devices and architectures is predicated largely on their physical performanceareal density, speed of operation, and consumed energy as benchmarked in [8,9]. These ultimately translate into processing throughput and consumed power of the chips, which are of utmost importance to the user. A fair comparison between the published neural network implementations is difficult due to the difference in the process technology generation, the network architectures, and computing workloads.The main purpose of the paper is to establish a methodology for comparing various neural network hardware approaches and to understand the trends revealed through its development. In doing that we strive to adhere to the following principles: a) general: wide scope of technologies, devices and circuits; b) transparent: simple analytics more important than precise simulations; c) uniform: consistent inputs and assumptions across multiple types of hardware; d) transparent: all models used are described and the code is available [10] to the reader for verification.Let us differentiate this work from the existing body of literature. We do not aim to give a literature review, and refer the reader to the excellent review papers in the neuromorphic hardware field [11,12] which do not attempt to quantitatively compare prior works, as we do in this paper. Oftentimes benchmarking refers to comparing various algorithms for an application mainly based on their accuracy and with little reference to hardware implementation, e.g. [13]. In contrast, we compare different types of hardware implementing the same algorithm and focusing on its energy consumption and performance.The discussion of neural networks in the numerous papers currently being published remains at the architecture level. For example, the accuracy of recognition...

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NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning

Cited by 392 publications

References 37 publications

DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies

DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies

Controlled Ionic Tunneling in Lithium Nanoionic Synaptic Transistor through Atomically Thin Graphene Layer for Neuromorphic Computing

Benchmarking Delay and Energy of Neural Inference Circuits

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