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Multiple logic devices are presently under study within the Nanoelectronic Research Initiative (NRI) to carry the development of integrated circuits beyond the CMOS roadmap. Structure and operational principles of these devices are described. Theories used for benchmarking these devices are overviewed, and a general methodology is described for consistent estimates of the circuit area, switching time and energy. The results of the comparison of the NRI logic devices using these benchmarks are presented.

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A new benchmarking of beyond-CMOS exploratory devices for logic integrated circuits is presented. It includes new devices with ferroelectric, straintronic, and orbitronic computational state variables. Standby power treatment and memory circuits are included. The set of circuits is extended to sequential logic, including arithmetic logic units. The conclusion that tunneling field-effect transistors are the leading low-power option is reinforced. Ferroelectric transistors may present an attractive option with faster switching delay. Magnetoelectric effects are more energy efficient than spin transfer torque, but switching speed of magnetization is a limitation. The paper enables a better focus on promising beyond-CMOS exploratory devices.

The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage (V DD ). In this paper, using atomistic quantum models that are in agreement with experimental TFET devices, we are reviewing TFETs prospects at L G = 13 nm node together with the main challenges and benefits of its implementation. Significant power savings at iso-performance to CMOS are shown for GaSb/InAs TFET, but only for performance targets which use lower than conventional V DD . Also, P-TFET current-drive is between 1× to 0.5× of N-TFET, depending on choice of I OFF and V DD . There are many challenges to realizing TFETs in products, such as the requirement of high quality III-V materials and oxides with very thin body dimensions, and the TFET's layout density and reliability issues due to its source/drain asymmetry. Yet, extremely parallelizable products, such as graphics cores, show the prospect of longer battery life at a cost of some chip area.INDEX TERMS Tunnel field-effect transistor (TFET), steep-slope.

Magnonics is a budding research field in nanomagnetism and nanoscience that addresses the use of spin waves (magnons) to transmit, store, and process information. The rapid advancements of this field during last one decade in terms of upsurge in research papers, review articles, citations, proposals of devices as well as introduction of new sub-topics prompted us to present the first Roadmap on Magnonics. This a collection of 22 sections written by leading experts in this field who review and discuss the current status besides presenting their vision of future perspectives. Today, the principal challenges in applied magnonics are the excitation of sub-100 nm wavelength magnons, their manipulation on the nanoscale and the creation of sub-micrometre devices using low-Gilbert damping magnetic materials and its interconnections to standard electronics. To this end, magnonics offers lower energy consumption, easier integrability and compatibility with CMOS structure, reprogrammability, shorter wavelength, smaller device features, anisotropic properties, negative group velocity, non-reciprocity and efficient tunability by various external stimuli to name a few. Hence, despite being a young research field, magnonics has come a long way since its early inception. This Roadmap asserts a milestone for future emerging research directions in magnonics, and hopefully, it will inspire a series of exciting new articles on the same topic in the coming years.

Operation of the array of coupled oscillators underlying the associative memory function is demonstrated for various interconnection schemes (cross-connect, star phase keying and star frequency keying) and various physical implementation of oscillators (van der Pol, phase-locked loop, spin torque). The speed of synchronization of oscillators and the evolution of the degree of matching is studied as a function of device parameters. The dependence of errors in association on the number of the memorized patterns and the distance between the test and the memorized pattern is determined for Palm, Furber and Hopfield association algorithms.

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