Experimental Study of Etched Back Thermal Oxide for Optimization of the Si/High-k Interface

Barnett, Joel; Moumen, N.; Gutt, J.; Gardner, Mark; Huffman, C.; Majhi, P.; Peterson, John J.; Gopalan, Sundararaman; Foran, Brendan; Li, H.-J.; Lee, B.H.; Bersuker, G.; Zeitzoff, P.; Brown, George; Lysaght, P.; Young, C.D.; Murto, Robert W.; Huff, Howard R.

doi:10.1557/proc-811-e1.4

Cited by 23 publications

(6 citation statements)

References 3 publications

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“…16 CP measurements were performed by applying periodic trapezoidal pulses with a fixed rise/fall ͑t r / t f ͒ time and amplitude ͑V a ͒ to the gate. High-k gate dielectric transistors were fabricated on 200 mm p / p+ epitaxial SiϽ 100Ͼ wafers using a standard complementary metal-oxide-semiconductor process with 1000°C/10 s dopant activation anneal.…”

mentioning

confidence: 99%

Spatial distributions of trapping centers in HfO2∕SiO2 gate stacks

Heh¹,

Young²,

Brown³

et al. 2006

Applied Physics Letters

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A methodology to analyze charge pumping (CP) data, which allows positions of probing traps in the dielectric to be identified, was applied to extract the spatial profile of traps in SiO2∕HfO2 gate stacks. The results suggest that traps accessible by CP measurements in a wide frequency range, down to few kilohertz, are located within or near the interfacial SiO2 layer rather than in the bulk of the high-k film.

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confidence: 99%

Spatial distributions of trapping centers in HfO2∕SiO2 gate stacks

Heh¹,

Young²,

Brown³

et al. 2006

Applied Physics Letters

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“…The gate electrode was formed using CVD TiN capped with a 100-nm poly-Si layer. The details of the process can be found elsewhere [9]. The gate stacks used in this letter are designed to have a considerable amount of charge trapping to illustrate the merits of the proposed methodology.…”

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confidence: 99%

A Novel Bias Temperature Instability Characterization Methodology for High-$k$nMOSFETs

Heh¹,

Choi²,

Young³

et al. 2006

IEEE Electron Device Lett.

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The power law dependence of the threshold voltage shift (∆V th ) on stress time for high-k nMOSFETs is studied using a single-pulse I d −V g technique. The power law exponent value is found to be strongly affected by fast transient charge detrapping during the stress interruption time, which may result in an inaccurate lifetime prediction. A new analysis method that eliminates the impact of the stress interruption time is proposed to evaluate bias temperature instability in n-type high-k devices.Index Terms-Lifetime prediction, relaxation, single pulse, transient charge.T HE STRESS-TIME dependence of the threshold voltage shift (∆V th ) is commonly used to predict device lifetime. This dependence is usually described by the simple power law relationship (∆V th ∝ t n ). However, it has been observed that ∆V th relaxes during stress interruption for sense measurements in high-k nMOSFETs under bias temperature instability (BTI) stress [1]. This phenomenon is attributed to the fast charge-relaxation (detrapping) process that occurs within microseconds once the stress bias is removed [1]- [4]. Such fast charge relaxation raises questions about the validity of the conventional V th monitoring methodology during BTI stress and the subsequent accuracy of lifetime predictions of high-k nMOSFETs.To address the issue of charge relaxation during sense measurements in high-k devices, it has been suggested to monitor drain current (I d ) degradation during stress without interruption [5]. However, monitoring I d degradation at the stress voltage (i.e., in the I d saturation regime) does not directly provide ∆V th values, while sensing I d in the linear regime is inevitably accompanied by a delay associated with switching the gate bias from the stress voltage to the sense voltage. To minimize charge trapping/detrapping during sense measurements, the singlepulse I d −V g technique has been developed [6], [7] and applied in BTI studies [8]. The sense-measurement time (pulse time) as well as charge relaxation during measurement is dramatically reduced using this single-pulse I d −V g technique, compared to the conventional dc I d −V g method, as shown in Fig. 1. In this letter, the single-pulse I d −V g measurement with different pulse times is used to study the effect of charge relaxation Manuscript Fig. 1. Comparison of stress sense time scales using the conventional dc and the single-pulse I d −Vg measurement methods.during sense measurements on the measured ∆V th in the high-k devices. A new analysis method is then proposed to extract the intrinsic stress-time dependence of ∆V th measured using both the single-pulse and conventional dc I d −V g techniques.The devices used in this letter were fully processed nMOSFETs, fabricated using a standard CMOS process with a 1000-• C 10-s dopant activation anneal. The gate dielectric stack included a 3-nm atomic-layer-deposited (ALD) HfO 2 dielectric deposited on a 1-nm thermal SiO 2 . The gate electrode was formed using CVD TiN capped with a 100-nm poly-Si layer. The details of the proc...

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“…Two different interfacial layers, processed at different conditions (ISSG and Chem_O), were used to implement different quality of the IL oxide as it was reported earlier that ISSG oxide is of better quality than Chem_O in terms of defects (13). For all the samples considered in this study, HfO 2 film (3 and 5 nm) was deposited by ALD method using TEMA (Hf[N(CH 3 )(C 2 H 5 )] 4 ) precursors and O 3 oxidation (14). For the gate electrode, a 10 nm TiN metal gate was deposited by ALD at 530 0 C. The deposition rate of TiN film was 1.2 Ǻ for this process condition.…”

Section: Methodsmentioning

confidence: 99%

Correlation of Negative Bias Temperature Instability and Breakdown in HfO₂/TiN Gate Stacks

Rahim

Misra

2010

ECS Trans.

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Both negative bias temperature instability (NBTI) and time dependent dielectric breakdown (TDDB) are two major reliability issues for long term performance of high-k gate stacks. In this work, these two degradation mechanisms were extensively analyzed to explore any possible correlation in terms of defects formation. A variety of dielectric stacks were considered to perform NBTI and TDDB. It was observed that NBTI induced defects, generated at the interface and in the interfacial layer were somewhat identical to the defects that dominate the breakdown process.

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Experimental Study of Etched Back Thermal Oxide for Optimization of the Si/High-k Interface

Cited by 23 publications

References 3 publications

Spatial distributions of trapping centers in HfO2∕SiO2 gate stacks

Spatial distributions of trapping centers in HfO2∕SiO2 gate stacks

A Novel Bias Temperature Instability Characterization Methodology for High-$k$nMOSFETs

Correlation of Negative Bias Temperature Instability and Breakdown in HfO₂/TiN Gate Stacks

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Experimental Study of Etched Back Thermal Oxide for Optimization of the Si/High-k Interface

Cited by 23 publications

References 3 publications

Spatial distributions of trapping centers in HfO2∕SiO2 gate stacks

Spatial distributions of trapping centers in HfO2∕SiO2 gate stacks

A Novel Bias Temperature Instability Characterization Methodology for High-$k$nMOSFETs

Correlation of Negative Bias Temperature Instability and Breakdown in HfO2/TiN Gate Stacks

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Correlation of Negative Bias Temperature Instability and Breakdown in HfO₂/TiN Gate Stacks