This paper reports the first demonstration of dual high-k and dual metal gate (DHDMG) CMOSFETs meeting the device targets of 45nm low stand-by power (LSTP) node. This novel scheme has several advantages over the previously reported dual metal gate integration, enabling the high-k and metal gate processes to be optimized separately for N and PMOSFETs in order to maximize performance gain and process controllability. The proposed gate stack integration results in a symmetric short channel V t of ~±0.45V with >80% high field mobility for both N and PMOSFETs and significantly lower gate leakage compared to poly/SiON stack.
SEMATECH 2706 Montopolis Drive, Austin, TX 78741 1. IBM assignee, 2. Ti assignee, and 3. Freescale assignee ABSTRACT If Si (110) channel can be used for both nMOS and pMOS FinFET, the implementation of FinFET can be simplified significantly. Electron mobility degradation at Si(110) channel of finFET has been one of the major barriers in this path. We report a creative method to improve electron and hole mobilities using a novel metal electrode induced-strain engineering, which also features the effective workfunction tuning of single metal electrode on high-k dielectric. Compared to planar SOI devices, our optimized SOI FinFETs with metal/high-k stack showed high field mobility for a (110)/<110> nMOSFETs, which increased almost two times. By optimizing the workfunction and the strain effect, we achieved an I on of 930µA/µm and 680µA/µm for nMOSFETs and pMOSFETs without implementing any other stress engineering process.
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