Thermally stable, high-quality ultrathin (EOT = 13 A) CVD HfAlO gate dielectrics with poly-Si gate electrode have been investigated for the first time. Results demonstrate that while in situ doping with Al significantly increases the crystallization temperature of HfO 2 up to 900 C and improves its thermal stability, it also introduces negative fixed oxide charges due to Al accumulation at the HfAlO-Si interface, resulting in mobility degradation. The effects of Al concentration on crystallization temperature, fixed oxide charge density, and mobility degradation in HfAlO have been characterized and correlated.

We report the process module development results and device characteristics of dual metal gate CMOS with TaSiN and Ru gate electrodes on HfO 2 gate dielectric. The wet etch of TaSiN had a minimal impact on HfO 2 (∆EOT<1Å). A plasma etch process has been developed to etch Ru/TaN/Poly (PMOS) and TaSiN/Ru/TaN/Poly (NMOS) gate stacks simultaneously. Well behaved dual metal gate CMOS transistors have been demonstrated with L g down to 85nm.

No abstract

The process module development and device characteristics of dual metal gate complementary metal-oxide-semiconductor ͑CMOS͒ with TaSiN and Ru gate electrodes on HfO 2 dielectric are reported. Highly selective wet etch processes for various metal gate materials ͑TaSiN, TiN, and TaN͒ have been developed with a minimal impact on HfO 2 and HfSiON. A plasma etch process is developed to etch TaSiN and Ru dual metal gate stacks simultaneously on the same wafer. Well behaved dual metal gate CMOS transistors with gate length down to 85 nm have been demonstrated. This integration method is highly versatile and can be applied to various metal gate materials.

No abstract

No abstract

No abstract

This paper compares metal oxide semiconductor field effect transistor ͑MOSFET͒ characteristics of TiN metal gate deposited by atomic layer deposition ͑ALD͒ and chemical vapor deposition ͑CVD͒ on Hf-based high-k dielectrics. Despite many similarities between these two techniques, clear differences were found in device characteristics such as equivalent oxide thickness ͑EOT͒, mobility, dopant diffusion, and trap generation. ALD TiN results in a thicker EOT than CVD TiN due to its inherent purging cycle and higher process temperature, but it has a stronger resistance to dopant diffusion. The ALD TiN process also provides better interfacial characteristics, thus better device performance.TiN has been widely studied as a metal gate electrode due to its process maturity in back-end applications. 1-3 Various TiN deposition techniques, such as physical vapor deposition ͑PVD͒ and chemical vapor deposition ͑CVD͒, have been studied for front-end metal gate application. 4,5 CVD TiN is generally considered to be more suitable for metal gate processes, since PVD TiN tends to damage the underlying dielectric film and generates bulk and interface traps. 6,7 More recently, the atomic layer deposition ͑ALD͒ process has shown promising results because it causes less damage and has lower impurity levels. 8,9 Several previous reports suggest that ALD has a clear advantage over PVD. 8,10,11 However, there are not many studies directly comparing ALD and CVD TiN processes. Despite many similarities between these two techniques, we found clear differences in the device characteristics of metal oxide semiconductor field effect transistors ͑MOSFETs͒ with TiN metal gates prepared by the ALD and CVD methods. ExperimentalAn ozonated water clean was used as a surface treatment before depositing the gate dielectric. This surface treatment tends to grow 0.5-1 nm chemical oxide under deposited high-k dielectric. HfSiO was used as the gate dielectric except for several control wafers with SiO 2 . ALD was used for depositing HfSiO using the precursors Hf͓N͑CH 3 ͒C 2 H 5 ͔ 4 and Si͓N͑CH 3 ͒C 2 H 5 ͔ 4 with O 3 as the oxygen source. The resultant HfSiO had ϳ20% SiO 2 confirmed by Rutherford backscattering ͑RBS͒ analysis. Hf-rich HfSiO was chosen for the higher k value. A 10 nm TiN layer was prepared by ALD or CVD, which was subsequently capped by 150 nm amorphous Si. A conventional complementary metal oxide semiconductor ͑CMOS͒ flow was used with a 1000°C, 5 s rapid thermal anneal ͑RTA͒ after source/drain ͑S/D͒ implant. BF 2 with a 4 ϫ 10 15 cm −2 dose at 20 keV was implanted as the p + S/D. For the n-MOSFET, As with a 5 ϫ 10 15 cm −2 dose at 20 keV was implanted as the n + S/D. Table I compares the process details of CVD and ALD TiN. Tetrakis͑diethylamino͒titanium ͑TDEAT͒ and TiCl 4 were used as the precursors for CVD and ALD, respectively. The Ti/N ratio was close to one in both materials. Due to the metal organic precursor, the CVD TiN had a relatively high carbon concentration, while less than 1% Cl was found in the ALD TiN film. With each deposi...