Thickness optimization of the TiN metal gate with polysilicon-capping layer on Hf-based high-k dielectric

Bae, S.H.; Song, Seung-Chul; Choi, Kwang-Il; Bersuker, G.; Brown, George; Kwong, Dim‐Lee; Lee, Byoung Hun

doi:10.1016/j.mee.2005.11.010

Cited by 16 publications

(7 citation statements)

References 5 publications

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“…To improve thermal stability, a thin metal gate with a poly cap structure is widely used [31]. It has been reported that the thickness of the metal has a significant impact on device performance [32]. The significance of metal thickness is shown in Fig.…”

Section: Optimization Of Metal Gate Thicknessmentioning

confidence: 99%

High Performance Metal Gate CMOSFETs with Aggressively Scaled Hf-Based High-k

Song¹,

Zhang

Bae³

et al. 2006

ECS Trans.

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The optimization of MOSFET performance with Hf-based high-k and TiN metal gate is discussed. MOSFET performance and mobility of metal and poly gate on both high-k and SiO2 are compared. Optimization of the thickness and composition of Hf-silicate is discussed in terms of charge trapping and boron diffusion. The effect of metal gate thickness is also investigated. Appropriate dry and wet etch processes are found to effectively eliminate the metal foot and high-k undercut. Impressive Ion- Ioff characteristics have been achieved by applying an optimized gate-first CMOS flow to the high-k/metal stack. Ion = 1100µA/µm and 540µA/µm was attained for N and PMOSFETs with Vdd = 1.2V and Ioff = 100nA/µm.

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Section: Optimization Of Metal Gate Thicknessmentioning

confidence: 99%

High Performance Metal Gate CMOSFETs with Aggressively Scaled Hf-Based High-k

Song¹,

Zhang

Bae³

et al. 2006

ECS Trans.

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“…10 During the screening phase of metal gate/high-k dielectrics, TiN drew attention because this material is already used in conventional CMOS fabrication. [11][12][13][14][15][16][17] In addition, the TiN has been used to integrate high-k/metal gate metal oxide semiconductor field-effect transistors ͑MOSFETs͒. [18][19][20][21][22] Wet etch is extensively used in CMOS technology; therefore, a controlled wet etch of TiN is very important.…”

mentioning

confidence: 99%

Deposition Method-Induced Stress Effect on Ultrathin Titanium Nitride Etch Characteristics

Hussain¹,

Quevedo‐Lopez

Alshareef

et al. 2006

Electrochem. Solid-State Lett.

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A systematic study to investigate the fundamental cause for wet etch variation of ultrathin titanium nitride ͑TiN͒ film as a function of the deposition technique such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition is presented. For this study, 10 nm TiN films were investigated using X-ray diffraction, X-ray photoelectron spectroscopy, X-ray reflectometry, and absolute ellipsometry. It is shown that the deposition method plays an important role on the final TiN crystallography and properties. However, it is demonstrated that the dominating factor defining etch rate is the resulting film strain.Thermodynamic stability, 1 low diffusivity, and high conductivity make titanium nitride ͑TiN͒ a good candidate for several complementary metal oxide semiconductor ͑CMOS͒ applications. In fact, TiN is already used in several applications in semiconductor device technology, such as aluminum ͑Al͒ diffusion barriers, advanced metallization, and interconnects in ultralarge scale integration ͑ULSI͒ circuits and devices. 2 TiN provides an effective barrier layer in contact strucrures 3 with exceptional stability due to the low diffusivity of impurity atoms in TiN. 4 Additionally, the low resistivity of TiN permits its use as a local interconnect in very large scale integration ͑VLSI͒ CMOS technology. 5 Also, the barrier height of TiN on silicon ͑Si͒ is about one-half of the energy gap, allowing the use of TiN contacts equally well on both p-and n-type silicon. 6 This also makes TiN a good midgap metal gate electrode. In addition, TiN has also been used as a good contact etch stop layer 7 and as an adhesion layer. 8 As reported elsewhere, a metal/high permittivity ͑k͒ dielectric combination is likely to replace the conventional poly silicon/silicon dioxide ͑SiO 2 ͒ gate stack. 9 The metal gate/high-k combination eliminates poly depletion, boron penetration, and instability of poly silicon/high-k dielectric combinations. 10 During the screening phase of metal gate/high-k dielectrics, TiN drew attention because this material is already used in conventional CMOS fabrication. [11][12][13][14][15][16][17] In addition, the TiN has been used to integrate high-k/metal gate metal oxide semiconductor field-effect transistors ͑MOSFETs͒. [18][19][20][21][22] Wet etch is extensively used in CMOS technology; therefore, a controlled wet etch of TiN is very important. 23,24 TiN can be etched by standard cleaning agent 1 ͓SC1ϭdeionized water:H 2 O 2 :NH 4 OH͔. A challenging task in dual metal gate CMOS integration with metal wet etch is that the etch needs to be effective to remove the metal gate electrode and, at the same time, highly selective to stop at the ultra-thin ͑typically 2-3 mm͒ high-k dielectric layer. 25 Furthermore, an over etch is normally used which might also result in additional high-k degradation. 26 Depending on the application, TiN can be deposited by chemical vapor deposition ͑CVD͒, physical vapor deposition ͑PVD͒, or atomic layer deposition ͑ALD͒ methods. Therefore, understanding the impac...

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“…Increasing the TiN content has several advantages. In reality, as reported in [ 13 , 14 ], increasing the TiN content can be effective to block boron penetration, thereby reducing interface defects and resistance. It is known that the degree of V th distribution decreases as the boron penetration decreases (which may be beneficial).…”

Section: Resultsmentioning

confidence: 97%

“…TiN engineering (e.g., by controlling the thickness of TiN) was carried out to suppress the gate leakage current. However, the unstable membranes of the thin TiN layer would be likely to increase the gate leakage current, and, thus, a thick TiN is thought to be a better choice in preventing the formation of interfacial traps, such as oxygen void diffusion and boron penetration [ 13 ]. In particular, it improves the threshold voltage ( V th ) distribution of p-type field-effect transistors (PFETs), and it is known to effectively improve the reliability, such as the bias temperature instability (BTI) [ 14 ].…”

Section: Introductionmentioning

confidence: 99%

Gate-Stack Engineering to Improve the Performance of 28 nm Low-Power High-K/Metal-Gate Device

2021

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In this study, a gate-stack engineering technique is proposed as a means of improving the performance of a 28 nm low-power (LP) high-k/metal-gate (HK/MG) device. In detail, it was experimentally verified that HfSiO thin films can replace HfSiON congeners, where the latter are known to have a good thermal budget and/or electrical characteristics, to boost the device performance under a limited thermal budget. TiN engineering for the gate-stack in the 28 nm LP HK/MG device was used to suppress the gate leakage current. Using the proposed fabrication method, the on/off current ratio (Ion/Ioff) was improved for a given target Ion, and the gate leakage current was appropriately suppressed. Comparing the process-of-record device against the 28 nm LP HK/MG device, the thickness of the electrical oxide layer in the new device was reduced by 3.1% in the case of n-type field effect transistors and by 10% for p-type field effect transistors. In addition, the reliability (e.g., bias temperature instability, hot carrier injury, and time-dependent dielectric breakdown) of the new device was evaluated, and it was observed that there was no conspicuous risk. Therefore, the HfSiO film can afford reliable performance enhancement when employed in the 28 nm LP HK/MG device with a limited thermal budget.

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Thickness optimization of the TiN metal gate with polysilicon-capping layer on Hf-based high-k dielectric

Cited by 16 publications

References 5 publications

High Performance Metal Gate CMOSFETs with Aggressively Scaled Hf-Based High-k

High Performance Metal Gate CMOSFETs with Aggressively Scaled Hf-Based High-k

Deposition Method-Induced Stress Effect on Ultrathin Titanium Nitride Etch Characteristics

Gate-Stack Engineering to Improve the Performance of 28 nm Low-Power High-K/Metal-Gate Device

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