Impact of Metal Gate Deposition Method on Characteristics of Gate-First MOSFET with Hf-Silicate

Abstract

This paper compares metal oxide semiconductor field effect transistor ͑MOSFET͒ characteristics of TiN metal gate deposited by atomic layer deposition ͑ALD͒ and chemical vapor deposition ͑CVD͒ on Hf-based high-k dielectrics. Despite many similarities between these two techniques, clear differences were found in device characteristics such as equivalent oxide thickness ͑EOT͒, mobility, dopant diffusion, and trap generation. ALD TiN results in a thicker EOT than CVD TiN due to its inherent purging cycle and higher process temperature, but it has a stronger resistance to dopant diffusion. The ALD TiN process also provides better interfacial characteristics, thus better device performance.TiN has been widely studied as a metal gate electrode due to its process maturity in back-end applications. 1-3 Various TiN deposition techniques, such as physical vapor deposition ͑PVD͒ and chemical vapor deposition ͑CVD͒, have been studied for front-end metal gate application. 4,5 CVD TiN is generally considered to be more suitable for metal gate processes, since PVD TiN tends to damage the underlying dielectric film and generates bulk and interface traps. 6,7 More recently, the atomic layer deposition ͑ALD͒ process has shown promising results because it causes less damage and has lower impurity levels. 8,9 Several previous reports suggest that ALD has a clear advantage over PVD. 8,10,11 However, there are not many studies directly comparing ALD and CVD TiN processes. Despite many similarities between these two techniques, we found clear differences in the device characteristics of metal oxide semiconductor field effect transistors ͑MOSFETs͒ with TiN metal gates prepared by the ALD and CVD methods. ExperimentalAn ozonated water clean was used as a surface treatment before depositing the gate dielectric. This surface treatment tends to grow 0.5-1 nm chemical oxide under deposited high-k dielectric. HfSiO was used as the gate dielectric except for several control wafers with SiO 2 . ALD was used for depositing HfSiO using the precursors Hf͓N͑CH 3 ͒C 2 H 5 ͔ 4 and Si͓N͑CH 3 ͒C 2 H 5 ͔ 4 with O 3 as the oxygen source. The resultant HfSiO had ϳ20% SiO 2 confirmed by Rutherford backscattering ͑RBS͒ analysis. Hf-rich HfSiO was chosen for the higher k value. A 10 nm TiN layer was prepared by ALD or CVD, which was subsequently capped by 150 nm amorphous Si. A conventional complementary metal oxide semiconductor ͑CMOS͒ flow was used with a 1000°C, 5 s rapid thermal anneal ͑RTA͒ after source/drain ͑S/D͒ implant. BF 2 with a 4 ϫ 10 15 cm −2 dose at 20 keV was implanted as the p + S/D. For the n-MOSFET, As with a 5 ϫ 10 15 cm −2 dose at 20 keV was implanted as the n + S/D. Table I compares the process details of CVD and ALD TiN. Tetrakis͑diethylamino͒titanium ͑TDEAT͒ and TiCl 4 were used as the precursors for CVD and ALD, respectively. The Ti/N ratio was close to one in both materials. Due to the metal organic precursor, the CVD TiN had a relatively high carbon concentration, while less than 1% Cl was found in the ALD TiN film. With each deposi...

High Performance Metal Gate CMOSFETs with Aggressively Scaled Hf-Based High-k

“…The dielectric EOT of the device increases as the TiN layer becomes thicker. This is caused by a trace amount of oxygen in the ALD TiN process [34]. This added oxygen thickens the bottom interfacial layer, increasing EOT.…”

“…The typical wet etch step used for high-k removal presents its own challenge. The conventional HF-based wet etch process tends to undercut high-k dielectric at the gate edge, especially when HfSiO or ultra thin HfO 2 is used [34]. The material that fills the undercut portion later in the process has a lower k value, which raises the EOT of the dielectric.…”

Dielectric dipole mitigated Schottky barrier height tuning using atomic layer deposited aluminum oxide for contact resistance reduction

“…treatment instead of HF grows %1 nm of chemically generated SiO 2 (Chem-SiO 2 ),20 (3) atomic layer deposition SiO 2 of %1 nm (ALD-SiO 2 ),[21][22][23] and (4) interfacial SiO 2 growth from the H-Si surface during ALD deposition of AlO x (IFL-SiO 2 ). 24,25 AlO x was deposited using trimethylaluminum precursor (TMA) with three processes: 4-cycles (AlO x -A) with 0.2 s TMA pulse length, 4-cycles (AlO x -B) with the first and second pulse of TMA extended to 2 s and 0.4 s in length, respectively, to reduce incubation phenomena, and 9-cycles (AlO x -C) with 0.2 s TMA pulse length.…”

Deposition Method-Induced Stress Effect on Ultrathin Titanium Nitride Etch Characteristics

“…10 During the screening phase of metal gate/high-k dielectrics, TiN drew attention because this material is already used in conventional CMOS fabrication. [11][12][13][14][15][16][17] In addition, the TiN has been used to integrate high-k/metal gate metal oxide semiconductor field-effect transistors ͑MOSFETs͒. [18][19][20][21][22] Wet etch is extensively used in CMOS technology; therefore, a controlled wet etch of TiN is very important.…”