Integration of dual metal gate CMOS with TaSiN (NMOS) and Ru (PMOS) gate electrodes on HfO/sub 2/ gate dielectric

Zhang, Z.B.; Song, Seok-Zun; Huffman, C.; Barnett, Joel; Moumen, N.; Alshareef, Husam N.; Majhi, P.; Hussain, Muhammad Mustafa; Akbar, M.S.; Sim, Johnny; Bae, S.H.; Sassman, B.; Lee, B.H.

doi:10.1109/.2005.1469208

Cited by 28 publications

(18 citation statements)

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“…Afterwards, the nMOS and pMOS gates are patterned [384]. There are different dual metal pairs for nMOS and pMOS applications, respectively, such as Ti vs Mo [382,385], TaSiN vs TiN [386], and TaSiN vs Ru [383]. In this deposition-etch-deposition approach, the major challenges are as follows: (1) Work function distance between n-Metal and p-Metal is not big enough for high-performance devices.…”

Section: Integration Of the Metal Gate Electrodes In Cmos Flowmentioning

confidence: 99%

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Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Zhu

Sun

et al. 2011

Progress in Materials Science

134

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Section: Integration Of the Metal Gate Electrodes In Cmos Flowmentioning

confidence: 99%

“…Two different metals, one suitable for nMOS and the other suitable for pMOS devices are selected. The conventional simple implementation of a dual metal gate is the deposition-etchdeposition approach [382,383]. Fig.…”

Section: Integration Of the Metal Gate Electrodes In Cmos Flowmentioning

confidence: 99%

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Zhu

Sun

et al. 2011

Progress in Materials Science

134

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“…Combined with the result of TaN on HfLaO as shown in the inset of Fig. 1, we show evidence that the incorporation of La can release Fermi level pinning between metal and HfO 2 dielectric, causing EWF shifts from midgap 4.64 [13] to 5.2 eV for p-metal Ru, and from 4.4 [8] to 3.9 eV for n-metal TaN, respectively. A specific model has been proposed to explain these phenomena [14], where the change of the metal EWF is attributed not only to the oxygen vacancy density in the high-κ layer, but also the difference in electronegativities of the materials involved in the gate stacks.…”

Section: Methodsmentioning

confidence: 69%

Widely Tunable Work Function TaN/Ru Stacking Layer on HfLaO Gate Dielectric

Wang

Hónɡ

et al. 2008

IEEE Electron Device Lett.

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For the first time, we demonstrate experimentally that using HfLaO high-κ gate dielectric and vertical stacks of TaN/Ru metal layers, dual metal gates with continuously tunable work function over a very wide range from 3.9 to 5.2 eV, can be achieved after 1000 • C annealing required by a conventional CMOS source/drain activation process. The wide tunability of work function for this bilayer metal structure is attributed to metal interdiffusion during annealing and the release of Fermi level pinning between metal gates (Ru and TaN) and HfLaO. Moreover, this change is thermally stable and unaffected by a subsequent high temperature process.Index Terms-CMOS, Fermi level pinning, HfLaO, high-κ dielectric, interdiffusion, metal gate, work function.

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“…Although TaSiN (nMOS), TiN (pMOS), and Ru (pMOS) on HfO 2 have been demonstrated in CMOS integration [45,46], the use of dual metal gates must address the significant complexity of optimizing two different metal etch processes. A single metal gate approach for CMOS integration provides several advantages over the dual metal electrode process, specifically a more straightforward integration and less demanding gate etching process optimization and control.…”

Section: Dielectric Capping For Work Function Tuningmentioning

confidence: 99%

The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies

Tseng¹

2010

Solid State Circuits Technologies

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Introduction Motivation for implementing high dielectric constant gate dielectric for advanced CMOS scalingSemiconductor devices need to have good performance, with a low cost and low power dissipation. For decades, research and development of semiconductor processing technology and device integration have focused on enhancing performance and reducing costs using SiO 2 as the gate dielectric and doped polysilicon as the gate electrode. The most effective way to enhance performance and reduce costs is to scale the device gate length and gate oxide. Scaling the gate length results in fabricating more devices per wafer (i.e., increase the device density) and thus reduce the cost per chip, while scaling the gate oxide enhances the drive current and reduces the short channel effects due to gate length scaling. However, as the gate oxide becomes thinner, the power to operate transistors increases because of greater gate oxide leakage current. To resolve this high gate oxide leakage problem, the mechanism of the carriers tunneling through the gate dielectric must be better understood. In an ideal metal-insulator-semiconductor (MIS) device, the current conduction in the insulator should be zero. In a real MIS device, however, current can flow through the insulating film by various conduction mechanisms. The two primary conduction mechanisms for electron tunneling through high quality gate dielectric are discussed below. Direct tunnelingIn a metal-insulator-semiconductor (MIS) stack, when the oxide voltage (V ox ) is smaller than the metal-insulator barrier height, the electron tunnels directly from the metal electrode into other semiconductor electrode through the insulator. This is known as the direct tunneling process. The equation for direct tunneling current density (current normalized by device area) is proportional to

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Integration of dual metal gate CMOS with TaSiN (NMOS) and Ru (PMOS) gate electrodes on HfO/sub 2/ gate dielectric

Cited by 28 publications

References 0 publications

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Widely Tunable Work Function TaN/Ru Stacking Layer on HfLaO Gate Dielectric

The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies

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