Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Scaling Effect on Parameters of HfO2 Based CSDG MOSFET

“…This is due to the variations in grain size (10 µm) and orientation of crystallographic structure. The leakage current increases with the grain boundaries of crystallized films [18]. This effect can be minimized in the HfO 2 based CSDG MOSFET due to the availability of SiO 2 .…”

“…It can also be achieved with the same equivalent oxide thickness (EOT) which has been discussed in the following sections. Due to high thickness in the design, the reliability of oxide layers can be enhanced [18]. Scaling of the solid state devices improves the performance and power of the system.…”

Identification of current transport mechanism in Al2O3 thin films for memory applications

“…Over the past few decades, the key to the continuous improvement in the performance of the ''work horse'' of the semiconductor industry, i.e., MOSFET has been scaling (Wilk et al 2001;He et al 2011;Robertson 2006). In 1974, when Robert Dennard and his team (Dennard et al 1974) proposed a set of rules to scale the various device parameters for improved performance, little did they know that it will revolutionize the silicon industry.…”

“…Hence, the ICs essentially remained a Si-based CMOS technology. However, as scaling continues, (a) SiO 2 , used as the gate dielectric, approaches its fundamental limit on physical thickness causing an increase in gate leakage current due to direct tunneling (He et al 2011, Lee et al 2006, Kim and Lee 2005, (b) shortchannel effects start to dominate (Lee et al 2006) and (c) current lithographic methods are challenged with the need of light sources with shorter wavelengths (Robertson 2006), thus questioning the device reliability at lower technology nodes and halting any improvement in the device performance. As performance enhancement through geometrical scaling becomes more challenging and demand for higher functionality increases, there is tremendous interest and potential to explore alternative gate stack technology, namely the high-j dielectrics (Wilk et al 2001).…”

“…Over the last decade, traditional SiO 2 has been replaced with SiO x N y and then Hf-based high-j gate dielectrics in an effort to reduce the excessive tunneling leakage current at the gate (Robertson 2006, Lee et al 2006, Kim and Lee 2005. Some of the critical requirements of a gate dielectric include (Wilk et al 2001, He et al 2011, Robertson 2006, Jones et al 2005, (a) thermal stability to withstand the high-temperature CMOS process flow, (b) high-quality silicon-insulator interface, (c) high band offset with Si to reduce carrier injection, d) high 'j' value to support future scaling of the gate dielectric and (e) low gate leakage.…”