A Novel Electrode-Induced Strain Engineering for High Performance SOI FinFET utilizing Si (1hannel for Both N and PMOSFETs

Abstract

SEMATECH 2706 Montopolis Drive, Austin, TX 78741 1. IBM assignee, 2. Ti assignee, and 3. Freescale assignee ABSTRACT If Si (110) channel can be used for both nMOS and pMOS FinFET, the implementation of FinFET can be simplified significantly. Electron mobility degradation at Si(110) channel of finFET has been one of the major barriers in this path. We report a creative method to improve electron and hole mobilities using a novel metal electrode induced-strain engineering, which also features the effective workfunction tuning of single metal electrode on high-k dielectric. Compared to planar SOI devices, our optimized SOI FinFETs with metal/high-k stack showed high field mobility for a (110)/<110> nMOSFETs, which increased almost two times. By optimizing the workfunction and the strain effect, we achieved an I on of 930µA/µm and 680µA/µm for nMOSFETs and pMOSFETs without implementing any other stress engineering process.

A comparative study of reliability and performance of strain engineering using CESL stressor and mechanical strain

“…4). With decreasing channel length, the hole mobility was enhanced more than the electron mobility, which was confirmed by piezoresistance (PR) calculation [8]. No differences in CV curve were observed with and without strain, indicating that equivalent oxide thickness and threshold voltage were not affected by the stressor layers (Fig.…”

Variability Analysis of TiN FinFET SRAM Cells and Its Compensation by Independent-DG FinFETs

“…This is explained by the WF lowering due to the composition or the thickness variation of the TiN gate. Previous reports show that the WF of the TiN gate is varied depending on the nitrogen concentration [13] or the TiN thickness [14]. In addition, by correlating other butterfly curves with the I-V characteristics of the FinFETs in each cell, it is concluded that the variation of the SRAM cell is due to the V th variation caused by the WFV.…”

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

“…It was reported that metal gate material deposited on top of the high-K dielectric can be made either compressive or tensile depending on the materials and the deposition conditions [51]. Owing to the close proximity of the metal films to the channel of transistors, significant amount of strain can be transferred into the channel, and therefore, additional performance benefit can be achieved by engineering MGS.…”