This paper addresses the design, implementation, and characterization of a novel highdensity Triple Gate Transistor in a 40 nm embedded Non-Volatile Memory technology. Deep trenches are used to integrate two vertical transistors connected in parallel with the main planar transistor. Thanks to the built-in trenches, the proposed manufacturing process increases the transistor width without impacting its footprint. The voltage/current characteristics of a planar MOS structure are compared with the features of the new Triple Gate Transistor. The new architecture provides an improved driving capability, with an on-state drain current twice as high as its equivalent standard MOS, combined with a lower threshold voltage, suitable for low-voltage applications. Finally, the gate oxide and junction reliability are validated over the operating voltage range.
In this paper, we detail an experimental study of the hot electron Source Side Injection programming operation of the embedded Select in Trench Memory (eSTM™) cell. A complete set of electrical characterizations is carried out. A focus on the Select Gate bias to improve the programming window and the consumption is reported. Moreover, the impact of the Sense-to-Select distance, on the memory behavior is highlighted. These characteristics give us the keys to find the best tradeoff to program this cell. Finally, the optimized programming scheme is used to show the endurance up to 500k cycles, while the programming current is monitored. We report an energy consumption decrease during the cycling thanks to the Source Side Injection mechanism. This makes the eSTM™ cell suitable for low-power and scalable embedded applications.
The impact of CMOS post nitridation annealing (PNA) temperature on a 40nm embedded Flash reliability is studied. Electrical characterizations of the Flash tunnel oxide are carried out on single cell. These are used to explain the better results in terms of endurance and data retention obtained on a 512kB test chip with a lower annealing temperature. This result can be linked with the decrease of nitrogen in the bulk oxide, improving oxide wear out performance against electrical stress and stress induced leakage current (SILC). The on-chip characterization is, here, an invaluable tool to show the extrinsic behavior in the memory array and apply product-like stress.
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