Effect of AC stress on oxide TDDB and trapped charge in interface states

Rebuffat, B.; Masson, Pascal Le; Ogier, Jean-Luc; Mantelli, M.; Laffont, R.

doi:10.1109/isicir.2014.7029500

Cited by 5 publications

(3 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Moreover, measurements presented in this work could be reproduced using different plateau times, duty cycles, rise/fall times to be able to understand the effect of these parameters on device degradation and to optimize them. Finally, complementary measurements could be performed on test MOS capacitors to investigate the effect of short-pulsed electrical stress in terms of interface trap density [16] and stress induced leakage current (SILC), which are physical manifestations of oxide degradation that can lead to program/erase window closure in non-volatile memory devices.…”

Section: Discussionmentioning

confidence: 99%

See 1 more Smart Citation

Enhancement of flash memory endurance using short pulsed program/erase signals

Chiquet¹,

Postel-Pellerin²,

Tuninetti³

et al. 2016

ACTA IMEKO

View full text Add to dashboard Cite

The present paper proposes to investigate the effect of short pulsed Program/Erase signals on the functioning of Flash memory transistors. Usually, electrical operations related to said devices involve the application of single long pulses to various terminals of the transistor to induce various tunneling effects allowing the variation of the floating gate charge. According to the literature, the oxide degradation occurring after a number of electrical operations, leading to loss of performance and reliability, can be reduced by replacing DC stress by AC stress or by reducing the time spent under polarization by the MOS-based devices. After a brief presentation of the functioning of the Flash memory transistors tested in this work, the experimental setup used to replace standard electric signals with short pulses will be described. Electrical results showing the benefits of programming and erasing non-volatile memories with short pulses will then be presented.

show abstract

Section: Discussionmentioning

confidence: 99%

“…In order to achieve lower device degradation, allowing oxide relaxation during electrical stress is a common solution [5], [16]. It has been achieved in this study by increasing the delay between the short pulses constituting the signals applied to the control gate and the drain of the transistor.…”

Section: Effect Of Duty Cyclementioning

confidence: 99%

Enhancement of flash memory endurance using short pulsed program/erase signals

Chiquet¹,

Postel-Pellerin²,

Tuninetti³

et al. 2016

ACTA IMEKO

View full text Add to dashboard Cite

show abstract

“…However, the high electric field stress can also incur a reliability issue that traps and interface states will be generated by the tunneling electron after gaining enough energy from the stressing electric field. [17,19] As a result, the reliability of the memory cell may be lowered.…”

Section: -2mentioning

confidence: 99%

Total Ionizing Dose Effects of 55-nm Silicon-Oxide-Nitride-Oxide-Silicon Charge Trapping Memory in Pulse and DC Modes

Li¹,

Bi²,

Xu³

et al. 2018

Chinese Phys. Lett.

View full text Add to dashboard Cite

The 60Co-γ ray total ionizing dose radiation responses of 55-nm silicon-oxide-nitride-oxide-silicon (SONOS) memory cells in pulse mode (programmed/erased with pulse voltage) and dc mode (programmed/erased with direct voltage sweeping) are investigated. The threshold voltage and off-state current of memory cells before and after radiation are measured. The experimental results show that the memory cells in pulse mode have a better radiation-hard capability. The normalized memory window still remains at 60% for cells in dc mode and 76% for cells in pulse mode after 300 krad(Si) radiation. The charge loss process physical mechanisms of programmed SONOS devices during radiation are analyzed.

show abstract