A Novel Trench-Based Triple Gate Transistor With Enhanced Driving Capability

Abstract

This paper addresses the design, implementation, and characterization of a novel highdensity Triple Gate Transistor in a 40 nm embedded Non-Volatile Memory technology. Deep trenches are used to integrate two vertical transistors connected in parallel with the main planar transistor. Thanks to the built-in trenches, the proposed manufacturing process increases the transistor width without impacting its footprint. The voltage/current characteristics of a planar MOS structure are compared with the features of the new Triple Gate Transistor. The new architecture provides an improved driving capability, with an on-state drain current twice as high as its equivalent standard MOS, combined with a lower threshold voltage, suitable for low-voltage applications. Finally, the gate oxide and junction reliability are validated over the operating voltage range.

Gate stress reliability of a novel trench-based Triple Gate Transistor

“…2c show TEM cross-section views of the TGT in width (W) and length (L) directions respectively. Based on these figures, we can see that the proposed 3D structure can be used to build an area-efficient transistor with a high driving capability compared to classical planar MOS transistor [5].…”

“…The studied device follows this trend: two lateral conduction channels controlled by vertical trenches filled with polysilicon are added to the main planar transistor. This arrangement results in a novel Triple Gate Transistor (TGT) which proposes an improved driving capability combined with a minimal footprint compared to conventional MOS transistors [5]. However, the TGT fabrication process includes the etching of deep trenches and the growth of a thin oxide around the trenches profile.…”

AC stress analysis of trench-based multi-gate transistors in a 40 nm e-NVM technology

“…The drain, source and bulk terminals are connected to the ground during the gate stress. As discussed in [15], PG and TG cannot support the same stress voltage because the vertical oxide thickness slightly decreases down to the sidewalls, which makes it more sensitive compared to the planar oxide. Moreover, the tip of the planar gate between the active and trench gate regions locally enhances the electric field (Fig.…”

“…These multi-gate structures have been fabricated to improve the driving capability with a low impact on the area of planar transistors used in column decoders to address the memory cells. A description of the functioning and performances of these devices are presented in [15] [16]. The MGT architecture design is based on a typical planar MOS transistor to which two lateral conduction channels are added by integrating deep trench transistors alongside the planar one between source and drain regions.…”