A novel True Random Number Generator circuit fabricated in a 130nm HfO2-based resistive RAM process is presented. The generation of the random bit stream is based on a specific programming sequence applied to a dedicated memory array. In the proposed programming scheme, all the cells of the memory array are addressed at the same time while the current provided to the circuit is limited to program only a subset of the memory array, resulting in a stochastic distribution of cell resistance values. Some cells are switched in a low resistive state, other cells are slightly programmed to reach an intermediate resistance state, while the remaining cells maintain their initial high resistance state. Resistance values are next converted into a bit stream and confronted to National Institute of Standards and Technology (NIST) test benchmarks. The generated random bit stream has successfully passed twelve NIST tests out of fifteen. Compared to state-of-the-art resistive RAM-based true random number generators, our proposed methodology is the first one to leverage on programming current limitation at a memory array level.

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We investigate the electron/hole trapping phenomena in alumina blocking oxide and their impact on the program/erase operations and retention of TaN/Al2O3/Si3N4/SiO2/Si (TANOS) memory devices. For this purpose, we perform simulations using a physical model that reproduces the charge injection/trapping in TANOS devices, which is extended in order to account for the charge trapping phenomena in the blocking layer. We derive the electrical characteristics of both electron and hole traps in Al2O3 by reproducing the measured program, erase, and retention transients. Our results show that the amount of electron charge trapped in the alumina during a program operation strongly depends on the stack composition and program voltages and can account for up to 25% of the total threshold voltage shift, whereas hole trapping during erase is negligible. Finally, we investigate the degradation of retention caused by the electron trapping in the alumina blocking layer, which is shown to result in an accelerated charge loss.

We present a detailed investigation of temperature effects on the operation of TaN/Al2O3/Si3N4/SiO2/Si (TANOS) memory devices. We show that not only retention but also program and erase operations are affected significantly by temperature. Using a large set of experimental data and simulations on a variety of TANOS stacks, we show that the temperature dependence of TANOS program and erase operations can be explained by accounting for that the alumina dielectric constant increases by 20%–25% over a 125 K temperature range.

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We perform experiments and device simulations to investigate the origin of current-voltage (I-V) linearity of TaO x-based resistive switching memory (RRAM) devices for their possible application as electronic synapses. By using electrical characterization and simulations, we link the electrical characteristics (linear or nonlinear I-V) to the microscopic properties of the conductive filament (CF). Our findings indicate that the shape and the thermal properties of the CF region are crucial to achieve linear I-V characteristics. These results allow optimizing the I-V curve linearity of TaO x-based RRAM devices, explaining the wide range of linear I-V characteristics experimentally observed on RRAM device obtained. When weight sum operation using SPICE simulations is performed, the read current is improved under the condition of linear I-V characteristics due to current loss minimization. INDEX TERMS I-V linearity, neuromorphic system, resistive switching memory (RRAM), TaO x .

We demonstrate that infrared femtosecond laser pulses with intensity above two-photon ionization threshold of crystalline silicon (c-Si) induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor (MOS) transistor devices. With repeated irradiations of Flash memory cells, we show how the laser-produced free-electrons naturally redistribute on both sides of the tunnel oxide until the electric field of the transistor is suppressed. This ability enables to determine in a nondestructive, rapid and contactless way the flat band and the neutral threshold voltages of the tested device. The physical mechanisms including nonlinear ionization, quantum tunneling of free-carriers, and flattening of the band diagram are discussed for interpreting the experiments. The possibility to control the carriers in memory transistors with ultrashort pulses holds promises for fast and remote device analyses (reliability, security, defectivity) and for new developments in the growing field of ultrafast microelectronics.