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This work reports the combined characterization at mountain altitude (on the ASTEP Platform at 2552 m) and at sealevel of more than ~50 Gbit of 90 nm NOR flash memories subjected to natural radiation (atmospheric neutrons). This wafer-level experiment evidences a limited impact of the terrestrial radiation at ground level on the memory SER evaluated without ECC. Experimental values are compared to estimations obtained from Monte Carlo simulation using the TIARA-G4 code combined with a physical model for charge loss in such floating-gate devices.

<p>We propose and develop a complete solution to evaluate very low leakage currents in Non‐Volatile Memories, based on the Floating‐Gate Technique. We intend to use very basic tools (power supply, multimeter,...) but with a very good current resolution. The aim of this work is to show the feasibility of such measurements and the ability to reach current levels lower than the ones obtained by any direct measurement, even from high‐performance devices. The key node is that the experiment is led in a very particular low‐noise environment (underground laboratory) allowing to keep the electrical contacts on the device under test as long as possible. We have demonstrated the feasibility of this approach and obtained a very promising 10^‐17A current level in less than two weeks.</p>

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In this paper the consumption of Flash Floating Gate cell, during a channel hot electron operation, is investigated. We characterize the device using different ramp and box pulses on control gate, to find the best solution to have low energy consumption and good cell performances and reliability. We use a new dynamic method to measure the drain current absorption in order to evaluate the impact of different bias conditions, and to study the cell behavior. The programming window and the energy consumption are considered as fundamental parameters. Using this dynamic technique, three zones of work are found; it is possible to optimize the drain voltage during the programming operation to minimize the energy consumption. Moreover, the cell's performances are improved using the CHISEL effect, with a reverse body bias. After the study concerning the programming pulses adjusting, we show the results obtained by increasing the channel doping dose parameter. Considering a channel hot electron programming operation, it is important to focus our attention on the bitline leakage consumption contribution. We measured it for the unselected bitline cells, and we show the effects of the lightly doped drain implantation energy on the leakage current. In this way the impact of gate induced drain leakage in band-to-band tunneling regime decreases, improving the cell's performances in a memory array.

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