Setting up of a floating gate test bench in a low noise environment to measure very low tunneling currents

Postel-Pellerin, J.; Micolau, G.; Chiquet, P.; Melkonian, J.; Just, G.; Boyer, Daniel; Ginoux, C.

doi:10.21014/acta_imeko.v4i3.251

Cited by 4 publications

(3 citation statements)

References 3 publications

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“…Indeed, they lead to use, for a very long time, huge, heavy and very expensive probers (mechanically insulated by air shocks), which is often economically not possible. The main idea of our experimental platform consists in developing a "cheap" platform, presented exhaustively with its methodology in [9][10][11][12]. The mechanical insulation is "naturally" done by the very peculiar environment of the underground LSBB Laboratory located in Apt (South of France).…”

Section: Floating Gate Techniquementioning

confidence: 99%

A global modeling approach of the leakage phenomena in dielectrics

et al. 2019

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Thanks to its low noise level, the LSBB environment provides particular environment to carry out high quality electrical characterizations. In this paper, we propose a complete modeling approach of the experimental results from our experimental microelectronic setup. The tested device is a Metal Oxide Semiconductor (MOS) floating gate capacitor which can be found in electrostatic non volatile memories such as Flash. The main idea is to characterize and model the leakage current through the tunnel oxide. We proposed, in a previous work, a model for charge loss considering a fractional Poisson process, involving only two parameters, expressed as a Mittag-Leffler (ML) function. Here, we also propose a combo of Fowler-Nordheim (FN) and Poole-Frenkel (PF) models for leakage currents, based on tunnel effect transport through the oxide. It gives the leakage current on a medium-to-long scale of time while the ML model can possibly take into account a shorter time step. The perspective is to find a relationship between these different models, used in various fields, to propose a generic model of phenomena involving leakage in complex and porous materials at different scales of time and space.

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Section: Floating Gate Techniquementioning

confidence: 99%

A global modeling approach of the leakage phenomena in dielectrics

et al. 2019

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“…To avoid as much as possible any movement around the test bench, a fully remote controlled experiment has been performed. The complete description of the test bench is given in [11] and improvements in the robustness of the technique can be found in [12].…”

Section: Proposed Test Benchmentioning

confidence: 99%

Toward an innovative stochastic modeling of electric charges loss through dielectric

et al. 2016

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Abstract. This paper deals with new stochastic modeling of very low tunneling currents in Non-Volatile Memories. For this purpose, we first develop current measurement method based on Floating Gate technique. In order to reach the long time behavior of electrical dynamic, we aim at using very basic tools (power supply, multimeter...) but still having a very good current resolution. Also, our measurement is led in a very particular lownoise environment (underground laboratory) allowing to keep the electrical contacts on the device under test as long as possible. After showing the feasibility of such measurements, we present a modeling approach of the charge loss process inside the Non-volatile Memories by using mathematical tool involving long memory effect. The model is based on stochastic counting process with memory effect yielding to a fractional relaxation equation for the charge loss over time. The main interest of the present model lies in the fact that the corresponding inversion problem involves only two parameters that can be carried out efficiently.

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“…Due to this functioning, the tunnel oxide layer, which can be degraded due to repeated electrical operations, is critical to the reliability of the memory devices and various solutions can be considered in order to improve their overall reliability [4]. The present work will focus on the use of short-pulsed signals, which consists in replacing long standard signals by a series of pulses with short plateau widths, as previous studies show that MOS-based devices are less impacted by AC stress than DC stress [5]- [11], or by shorter pulses of higher amplitude [12].…”

Section: Introductionmentioning

confidence: 99%

Enhancement of flash memory endurance using short pulsed program/erase signals

Chiquet¹,

Postel-Pellerin²,

Tuninetti³

et al. 2016

ACTA IMEKO

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The present paper proposes to investigate the effect of short pulsed Program/Erase signals on the functioning of Flash memory transistors. Usually, electrical operations related to said devices involve the application of single long pulses to various terminals of the transistor to induce various tunneling effects allowing the variation of the floating gate charge. According to the literature, the oxide degradation occurring after a number of electrical operations, leading to loss of performance and reliability, can be reduced by replacing DC stress by AC stress or by reducing the time spent under polarization by the MOS-based devices. After a brief presentation of the functioning of the Flash memory transistors tested in this work, the experimental setup used to replace standard electric signals with short pulses will be described. Electrical results showing the benefits of programming and erasing non-volatile memories with short pulses will then be presented.

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Setting up of a floating gate test bench in a low noise environment to measure very low tunneling currents

Cited by 4 publications

References 3 publications

A global modeling approach of the leakage phenomena in dielectrics

A global modeling approach of the leakage phenomena in dielectrics

Toward an innovative stochastic modeling of electric charges loss through dielectric

Enhancement of flash memory endurance using short pulsed program/erase signals

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