Nowadays, the study of physical mechanisms that occur during Flash memory cell life is mandatory when reaching the 40nm and beyond nodes in terms of reliability. In this paper we carry out a complete experimental method to extract the floating gate potential evolution during the cell aging. The dynamic current consumption during a Channel Hot Electron operation for a NOR Flash is a proper quantitative marker of the cell degradation. Here both drain and bulk currents are measured and monitored throughout the endurance tests. We coupled these characteristics with quasi-static measurements to correlate the cell degradation with an equivalent transistor. The final goal is to be able to split the physical effects of repetitive hot carrier and Fowler-Nordheim operations, typical of Flash memories, to extract the electrical parameters evolution on a simple equivalent transistor.

In this paper, we detail an experimental study of the hot electron Source Side Injection programming operation of the embedded Select in Trench Memory (eSTM™) cell. A complete set of electrical characterizations is carried out. A focus on the Select Gate bias to improve the programming window and the consumption is reported. Moreover, the impact of the Sense-to-Select distance, on the memory behavior is highlighted. These characteristics give us the keys to find the best tradeoff to program this cell. Finally, the optimized programming scheme is used to show the endurance up to 500k cycles, while the programming current is monitored. We report an energy consumption decrease during the cycling thanks to the Source Side Injection mechanism. This makes the eSTM™ cell suitable for low-power and scalable embedded applications.

The impact of CMOS post nitridation annealing (PNA) temperature on a 40nm embedded Flash reliability is studied. Electrical characterizations of the Flash tunnel oxide are carried out on single cell. These are used to explain the better results in terms of endurance and data retention obtained on a 512kB test chip with a lower annealing temperature. This result can be linked with the decrease of nitrogen in the bulk oxide, improving oxide wear out performance against electrical stress and stress induced leakage current (SILC). The on-chip characterization is, here, an invaluable tool to show the extrinsic behavior in the memory array and apply product-like stress.

The reliability requirements of Flash memory become more and more challenging. Flash memory technology development needs testchips to allow large statistical studies and a product-like approach. In this paper, we present a methodology of bitmap analysis to extract and follow the intrinsic and extrinsic parameters of a 40nm eFlash technology during ramp-up. This methodology is based first on analog bitmap acquisition on 512kB testchip, followed by correction of spatial variabilities like peripheral circuit influences, array organization impacts and process-induced effects, to extract supplementary cell electrical parameters such as threshold voltage, transconductance or programing window. Finally such an analysis tool enhances the advantageous properties of test chip, its large memory cell statistics and its product-like organization, to give more reliable data and yields more information about intrinsic cell technology weaknesses and the best way to tackle them when integrated at product level. I. Criteria Test structure Single device Test chip Statistics availability Low bits density High bits density Cell envirronement Limited Product like Memory defectivity Memory only Peripheral effect, memory array organization/ intersite variation Test time Low Need burn-in, or early failure binning (EWS) Test flexibility High. Limited by its embedded test modes (BIST, reliability test, DMA…) and register values.

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In this paper we present a full free addressable 4kb EEPROM memory array. This test structure based on CAST vehicle has been upgraded with flexible addressing logic to select any numbers of cells on single or multiple word lines. To this aim, column/row shift registers, to enable an easy cell biasing, have been implemented in an embedded non-volatile memory environment. High voltage circuits, driven by low voltage shift registers, are used to bias selected cells for electrical characterizations and reliability tests purposes. This kind of structure has been developed to improve the efficiency of electrical characterization laboratory, resulting in an enhanced acquisition with respect to standard CAST test techniques, opening the path to fine statistical analysis.

This paper assesses the 2.5D simulation method for limiting the electrodes debiasing of interdigitated devices. This method uses both spice and finite element method simulations where a resistance grid models the electrodes and a 2D finite elements structure models the device. A lateral 4H-SiC PiN diode has been selected for this study. In order to assess this method, 2.5D simulation method has been compared to 3D simulations.

In this work we present a method to find a correlation between the measurements on single 40nm embedded Flash memory cell, and the 512kB test chip electrical results. The bridge between these two structures is the cell array stress test (CAST). We are able to simulate the behavior of a 10kb and a 1Mb CAST structures. The parasitic resistances are taken into account, as well as, the testchip distributions for the modeling. The aim is to reduce the time of test obtaining preliminary information concerning the fabrication process and the memory yield at the parametric test level and before the electrical wafer sorting.