2021
DOI: 10.1016/j.microrel.2021.114265
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Hot-carrier evaluation of a zero-cost transistor developed via process optimization in an embedded non-volatile memory CMOS technology

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Cited by 5 publications
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“…This showed that created defects may be distributed over the entire surface of the dielectric and therefore can be used as a main tool for BD characterization and a global modelling of time to BD in Off-state mode. Indeed, only few investigations are given on effective electric field with VDS only, and on the Off-state current with gate-length LG [33][34][35][36][37][38]. Using the fact that applied electric field responsible for the oxide BD is strongly related to carrier energy and the amount of HC induced by II from the drain junction, we characterize roughly the impact of carrier energy by the peak electric field dependence Emax ≈ VDS/LG in thin gate-oxide structures, with same WG and variable gate-length.…”
Section: Currentsmentioning
confidence: 99%
“…This showed that created defects may be distributed over the entire surface of the dielectric and therefore can be used as a main tool for BD characterization and a global modelling of time to BD in Off-state mode. Indeed, only few investigations are given on effective electric field with VDS only, and on the Off-state current with gate-length LG [33][34][35][36][37][38]. Using the fact that applied electric field responsible for the oxide BD is strongly related to carrier energy and the amount of HC induced by II from the drain junction, we characterize roughly the impact of carrier energy by the peak electric field dependence Emax ≈ VDS/LG in thin gate-oxide structures, with same WG and variable gate-length.…”
Section: Currentsmentioning
confidence: 99%