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This paper addresses the design, implementation, and characterization of a novel highdensity Triple Gate Transistor in a 40 nm embedded Non-Volatile Memory technology. Deep trenches are used to integrate two vertical transistors connected in parallel with the main planar transistor. Thanks to the built-in trenches, the proposed manufacturing process increases the transistor width without impacting its footprint. The voltage/current characteristics of a planar MOS structure are compared with the features of the new Triple Gate Transistor. The new architecture provides an improved driving capability, with an on-state drain current twice as high as its equivalent standard MOS, combined with a lower threshold voltage, suitable for low-voltage applications. Finally, the gate oxide and junction reliability are validated over the operating voltage range.

This paper addresses the design and characterization of different architectures of novels highdensity multi-gate transistors manufactured in a 40 nm embedded Non-Volatile Memory technology. The proposed multi-gate architectures are based on vertical transistors integrated in deep trenches built alongside the main transistor. Thanks to the built-in trench, the proposed manufacturing process increases the transistor width without impacting its footprint. The electrical behaviour of the different multi-gate transistor architectures is studied and compared based on I-V characteristics. Relevant physical and electrical parameters such as the device footprint, the ON and OFF currents along with the threshold voltage and subthreshold slopes are extracted in order to determine the best candidate among the three studied architectures.

We report the fabrication of high performance singlepolysilicon npn bipolar transistors using a low cost 2 0 0 " 0.35pm bipolar technology. The devices feature record cut-off frequency and maximum oscillation frequency of 35GHz and 54GHz respectively, comparable to state-of-the-art results from more complex double-polysilicon bipolar processes.

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