Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology

Innocenti, J.; Welter, Loic; Julien, Franck; Lopez, L.; Sonzogni, J.; Niel, S.; Régnier, A.; Paire, Emmanuel; Labory, Karen; Denis, E.; Portal, J.M.; Masson, Pascal Le

doi:10.1109/mwscas.2014.6908560

Cited by 6 publications

(4 citation statements)

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“…where i s,n and i s,p are the NMOS and PMOS source currents, respectively. Thus, if f = 100 MHz, total average dynamic power dissipation can be estimated by integrating the voltage and current signals depicted in Figures 3 and 4 using Equation (5). This method will be used later on in the Results section.…”

Section: Methodsmentioning

confidence: 99%

“…The CMOS inverter circuit used to carry out this test is shown in Figure 2. The average dynamic power dissipation was calculated using Equation (5). Tables 6-8 show the average dynamic power dissipation for the three structures.…”

Section: Effect Of Varying the Operating Frequency With Discrete C Lmentioning

confidence: 99%

“…Several methods have been used to reduce dynamic power dissipation in both BULK and SOI transistors including reducing the supply voltage V DD , load capacitance C L , and the frequency f [5]. Another published methodology for reducing dynamic power dissipation at the circuit-level is by clustering a number of gates and making one single large sleep transistor responsible for them [3].…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, the size of the sleep transistor will get larger to compensate for the increased interconnect resistance. Innocenti et al [5] suggested decreasing the dynamic power dissipation caused by short circuit effect, using reduced transistor width. This technique reduced the dynamic power dissipation by 20% when the transistor width was reduced by 45%.…”

Section: Introductionmentioning

confidence: 99%

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TCAD Simulation and Analysis of Selective Buried Oxide MOSFET Dynamic Power

Mahmoud

Madathumpadical

Al‐Nashash

2019

JLPEA

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Low power consumption has become one of the major requirements for most microelectronic devices and systems. Increasing power dissipation may lead to decreasing system efficiency and lifetime. The BULK metal oxide semiconductor field-effect transistor (MOSFET) has relatively high power dissipation and low frequency response due to its internal capacitances. Although the silicon-on-insulator (SOI) MOSFET was introduced to resolve these limitations, other challenges were introduced including the kink effect in the current-voltage characteristics. The selective buried oxide (SELBOX) MOSFET was then suggested to resolve the problem of the kink effect. The authors have previously investigated and reported the characteristics of the SELBOX structure in terms of kink effect, frequency, thermal and static power characteristics. In this paper, we continue our investigation by presenting the dynamic power characteristics of the SELBOX structure and compare that with the BULK and SOI structures. The simulated fabrication of the three devices was conducted using Silvaco TCAD tools in 90 nm complementary metal oxide semiconductor (CMOS) technology. Simulation results show that the average dynamic power dissipation of the CMOS BULK, SOI and SELBOX are compatible at high frequencies with approximately 54.5 µW. At low frequencies, the SOI and SELBOX showed comparable dynamic power dissipation but with lower values than the BULK structure. The difference in power dissipation between the SELBOX and BULK is in the order of nano watts. This power difference becomes significant at the chip level. For instance, at 1 MHz, SOI and SELBOX exhibit an average dynamic power consumption of 0.0026 µW less than that of the BULK structure. This value cannot be ignored when a chip operates using thousands or millions of SOI or SELBOX MOSFETs.

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Section: Methodsmentioning

confidence: 99%

Section: Effect Of Varying the Operating Frequency With Discrete C Lmentioning

confidence: 99%